Chip-on-Film Semiconductor Package for Heat Dissipation and EMI Shielding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor packages in chip-on-film (COF) technology face challenges in heat dissipation and electromagnetic interference (EMI) management due to miniaturization and thinning of display apparatuses, which affect the performance and reliability of semiconductor chips.
Innovation Solution
A semiconductor package design featuring a base film with conductive structures on both surfaces, via connections, and capping layers that contact conductive patterns and pads, enhancing heat dissipation and electrical characteristics by improving thermal management and shielding against EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a semiconductor chip is mounted on a base film in a COF package, then the device can be miniaturized and thinned, but heat dissipation becomes insufficient and EMI increases
Solution Approach 1:
The patent introduces a dual-sided conductive structure with first and second conductive patterns on opposite surfaces of the base film, connected by vias. This three-dimensional arrangement transforms the traditional single-plane layout into a multi-layered configuration, enabling improved heat dissipation pathways and EMI shielding without increasing the device's footprint area.
Solution Approach 2:
The conductive patterns on both surfaces of the base film serve multiple functions simultaneously: they provide electrical connection pathways, act as heat dissipation structures, and function as EMI shielding elements. This multi-functionality allows the same structural elements to address multiple technical challenges arising from device miniaturization.
2Volume of moving object
If a semiconductor chip is mounted on a base film in a COF package, then the device can be miniaturized and thinned, but electromagnetic interference (EMI) increases
Solution Approach 1:
The patent utilizes the conductive patterns and capping layers to convert electromagnetic interference, normally a harmful effect, into a beneficial shielding mechanism. The conductive structures act as Faraday cages that redirect and dissipate EMI, protecting sensitive circuitry while maintaining the miniaturized form factor.
3Temperature
If conductive structures are added to improve heat dissipation and EMI shielding, then thermal management and electrical characteristics improve, but device complexity increases
Solution Approach 1:
The patent merges multiple functional requirements into integrated structures. The conductive patterns simultaneously serve as electrical interconnects, heat dissipation pathways, and EMI shielding elements. The capping layers combine protective, conductive, and thermal management functions, reducing the need for separate dedicated components and simplifying the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances heat dissipation and electrical performance, improving signal integrity and reducing EMI, thereby ensuring better operation of semiconductor chips in miniaturized and thinned display apparatuses.
Implementation Method 1
a via passing through the base film and connecting the first conductive structure to the second conductive structure
Implementation Method 2
the first conductive layer contacts a region of the first conductive pattern exposed by the first opening
Implementation Method 3
a second conductive layer disposed on the second surface of the base film and covering the second conductive structure, wherein a portion of the second conductive layer contacts at least a portion of the second conductive structure
Implementation Method 4
improving heat dissipation and electrical characteristics
Data Source
AI summary
A semiconductor package includes a base film, a first conductive structure disposed on a first surface of the base film, a second conductive structure disposed on a second surface of the base film, a via passing through the base film and connecting the first conductive structure to the second conductive structure, a semiconductor chip on the first surface and electrically connected to the first conductive structure, a first insulating layer covering the first conductive structure and including a first opening exposing a first conductive pattern of the first conductive structure, a first conductive layer disposed on the first insulating layer, covering the first insulating layer and the semiconductor chip, and contacting a region of the first conductive pattern exposed by the first opening, and a second conductive layer disposed on the second surface, covering the second conductive structure, and contacting at least a portion of the second conductive structure.