Chip-on-Film Package Structure for Thin-Panel Heat Dissipation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Recent display apparatuses require smaller bezels and thinner panels, necessitating improved process optimization and temperature control technology for semiconductor chips mounted on chip-on-film (COF) packages.
Innovation Solution
A COF package design that includes a semiconductor chip with external connection pads, a conductive portion with integrated conductive lines and via structures, a base film, and a protective layer, along with a heat dissipation member to efficiently manage temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If semiconductor chips are mounted on COF packages to enable smaller bezels and thinner panels, then panel thickness and bezel size are reduced, but temperature control and reliability of the semiconductor chips become problematic
Solution Approach 1:
A protective layer is introduced as an intermediary component between the semiconductor chip and the external environment. This protective layer covers the sidewalls and lower surface of the semiconductor chip, providing thermal insulation and protection while allowing the chip to be mounted on the COF package in a thin-profile configuration. The protective layer mediates between the need for thin panels and the need for chip reliability by providing a controlled thermal and protective environment.
Solution Approach 2:
The protective layer is applied beforehand to cover and protect the semiconductor chip's sidewalls and lower surface before the chip is fully integrated into the COF package. This prior protection ensures that the chip is shielded from thermal stress and environmental factors from the outset, maintaining reliability in the thin-panel configuration.
2Ease of manufacture
If conventional conductive lines and via structures are used to connect semiconductor chips on COF packages, then manufacturing processes are simpler, but bonding reliability and electrical connection stability are insufficient
Solution Approach 1:
The conductive line and via structure are merged into a single integrally formed conductive component. This integrated structure eliminates the need for separate bonding processes between distinct conductive line and via components, thereby maintaining manufacturing simplicity while significantly improving electrical connection reliability and stability through continuous conductive pathways without bonding interfaces.
Solution Approach 2:
The integrated conductive structure utilizes composite material formation techniques where the conductive line and via are formed as a unified structure with optimized material properties. This composite approach ensures both electrical conductivity and mechanical stability throughout the connection path, enhancing reliability without complicating the manufacturing process.
3Reliability
If the protective layer covers the entire semiconductor chip including the upper surface, then protection is maximized, but access to the chip's upper surface for electrical connections is blocked
Solution Approach 1:
The protective layer is applied with local quality differentiation - it covers the sidewalls and lower surface of the semiconductor chip to provide maximum protection in these regions, while deliberately leaving the upper surface exposed. This selective coverage ensures that protection is provided where most needed (sidewalls and lower surface exposed to environment) while maintaining access to the upper surface for electrical connections and bonding operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The COF package achieves improved reliability and efficient heat dissipation, addressing the need for smaller and thinner display panels while ensuring the stability and performance of semiconductor chips.
Implementation Method 1
a heat dissipation member arranged to correspond to the semiconductor chip and including a conductive material
Data Source
AI summary
A chip-on-film (COF) package includes a semiconductor chip comprising a plurality of external connection pads for connecting to outside of the semiconductor chip; a conductive portion electrically connected to the plurality of external connection pads; a base film attached to a lower end of the conductive portion and having an upper surface and a lower surface opposite each other; and a protective layer covering the conductive portion on the upper surface of the base film. The protective layer covers sidewalls and a lower surface of the semiconductor chip, and the conductive portion comprises a plurality of conductive lines disposed on the upper surface of the base film, and a plurality of via structures formed integrally with the plurality of conductive lines and electrically connected to the plurality of external connection pads.