Chip-on-Film Plating Layout for Uniform Bonding Pad Thickness
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Solution Overview
Problem
Existing COF packaging technologies face challenges in achieving high precision and uniform pad thickness due to concentrated power lines and high current density during electroplating, leading to poor bonding and non-uniform thickness of pads, which are critical for high-resolution 3D display products.
Innovation Solution
A chip on film design with accompanying plated patterns in peripheral areas to distribute power lines and current density evenly, ensuring uniform pad thickness by integrating these patterns with pads in the same layer and material, and using supporting patterns to balance bonding pressure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electroplating is used to form pads during COF packaging, then pads can be formed with good electrical conductivity, but concentrated power lines and high current density cause non-uniform pad thickness and poor bonding
Solution Approach 1:
The patent introduces accompanying plated patterns in peripheral areas with different plating thicknesses (5-10 μm) compared to bonding pads (3-5 μm). This local differentiation redistributes current density, preventing concentration at pad edges while maintaining uniform pad thickness for reliable bonding.
Solution Approach 2:
The accompanying plated patterns act as intermediary elements that mediate the electroplating process. By providing additional plating surfaces in peripheral areas, they serve as current distribution mediators that prevent direct current concentration on bonding pads, ensuring uniform thickness without compromising bonding quality.
2Productivity
If high current density is used during electroplating to increase plating speed, then productivity improves, but pad thickness uniformity deteriorates
Solution Approach 1:
The patent changes the geometric parameters of the plating structure by adding accompanying plated patterns in peripheral areas. This modifies the current distribution parameters during electroplating, allowing high current density to be applied without causing non-uniform pad thickness, thus maintaining both productivity and precision.
3Reliability
If bonding areas are increased to improve bonding reliability, then device area increases, but current density concentration worsens
Solution Approach 1:
The patent segments the plating structure into bonding pads in central bonding areas and accompanying plated patterns in peripheral areas. This segmentation separates the bonding function from the current distribution function, allowing large bonding areas to maintain reliability while peripheral segments prevent current density concentration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures uniform pad thickness and improved bonding yield, addressing the issues of non-uniformity and poor bonding in high-resolution COF packaging, suitable for high-density data transmission in 3D display products.
Implementation Method 1
concentrated power lines and high current density during electroplating
Implementation Method 2
using supporting patterns to balance bonding pressure
Data Source
AI summary
The present disclosure provides a chip on film and a display apparatus, the chip on film includes a base substrate, which includes: a plurality of bonding areas and a peripheral area arranged around the bonding areas; a plurality of bonding pads located on the base substrate, and each bonding area is provided with multiple bonding pads; and an accompanying plated pattern, which is located in a same layer and made of a same material as the plurality of bonding pads, and is located in a part of the peripheral area on at least one side of the bonding areas.