COF Semiconductor Package Support Pattern for Bonding Alignment
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Solution Overview
Problem
The thermal compression process in chip on film (COF) semiconductor packages leads to irregular shrinkage and misalignment due to undulation phenomena in the film substrate, causing inaccuracies in bonding with semiconductor devices.
Innovation Solution
Incorporating a support pattern on the lower surface of the film substrate that extends along the side surfaces, overlapping with pad openings, to generate uniform shrinkage and predict the rate of change of the film substrate, thereby preventing misalignment during the bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal compression process is used to bond metal lead portion and semiconductor chip, then bonding is achieved, but undulation phenomenon occurs on the film substrate causing irregular shrinkage and misalignment
Solution Approach 1:
The patent applies preliminary action by forming a support pattern on the film substrate before the thermal compression bonding process. This support pattern pre-compensates for the expected undulation and shrinkage that will occur during bonding, thereby maintaining alignment precision while achieving reliable bonding between the metal lead portion and semiconductor chip.
Solution Approach 2:
The patent employs parameter changes by modifying the physical structure of the film substrate through the addition of a support pattern. This pattern changes the mechanical parameters of the substrate, providing localized reinforcement that controls shrinkage characteristics and prevents undulation during the thermal compression process, thus resolving the contradiction between bonding reliability and alignment precision.
2Reliability
If film substrate is heated during thermal compression, then bonding is achieved, but irregular shrinkage occurs due to undulation phenomenon
Solution Approach 1:
The patent applies local quality by creating a support pattern with specific local reinforcement properties on the film substrate. This pattern provides localized structural support in regions prone to undulation and irregular shrinkage, allowing the substrate to maintain its shape stability during thermal compression while still achieving reliable bonding.
Solution Approach 2:
The patent employs composite materials by combining the film substrate with a support pattern made of different material properties. This composite structure leverages the flexibility of the film substrate for bonding while the support pattern material provides dimensional stability and resistance to irregular shrinkage during the heating and compression process.
3Manufacturing precision
If support pattern is added to prevent irregular shrinkage, then alignment precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the support function into a separate, distinct support pattern element on the film substrate. This segmented approach allows the support pattern to be independently designed and optimized for preventing irregular shrinkage, thereby improving alignment precision while keeping the overall device structure modular and manageable rather than overly complex.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The support pattern ensures uniform shrinkage of the film substrate, allowing for accurate prediction of its rate of change and mitigating misalignment issues during the bonding of semiconductor devices to the outer lead bonding portion.
Implementation Method 1
During the thermal compression process, the film substrate expands and then contracts due to high-temperature heat
Implementation Method 2
the support pattern generates uniform shrinkage and predicts the rate of change of the film substrate
Data Source
AI summary
A semiconductor package includes a film substrate; a plurality of wires on an upper surface of the film substrate; an upper insulating film covering the plurality of wires on the upper surface of the film substrate and defining a plurality of pad openings and a mounting region opening such that, the plurality of pad openings expose at least a portion of an outer lead bonding portion of the plurality of wires along at least one of the first side surface or the second side surface and the mounting region opening exposes at least a portion of an inner lead bonding portion of the plurality of wiring; a semiconductor chip bonded to and electrically connected to the exposed inner lead bonding portion, and at least one support pattern on a lower surface of the film substrate and extending in the first direction to overlap with the plurality of pad openings.