COF Wiring Contact Layout for Bump Connection Reliability
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Solution Overview
Problem
Existing semiconductor packages face challenges in ensuring reliability due to issues such as line disconnection and contact failure between wiring lines and bumps, particularly in flexible film substrates used in chip-on-film (COF) packages for smaller, thinner, and lighter electronic devices.
Innovation Solution
The semiconductor package design includes a first wiring line with a contact portion that varies in width, featuring a narrower initial section and a wider section further away from the connection pad, and a bump structure that enhances contact stability, preventing separation and crack formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a wiring line is made thin to reduce package size, then the package can be smaller and lighter, but the wiring line becomes more prone to disconnection and contact failure
Solution Approach 1:
The wiring line is designed with varying width along its length, with the contact portion having a greater width than other portions. This local quality change reinforces the critical contact area between the wiring line and bump while maintaining thin wiring lines in non-critical areas, thus preserving both small package size and contact reliability
Solution Approach 2:
The wiring line is segmented into different portions with different widths - a narrower main body and a wider contact portion. This segmentation allows the wiring line to be thin overall for small package size while having a locally reinforced contact area for improved reliability
2Reliability
If the contact portion width is increased to prevent line disconnection, then contact stability improves, but the overall wiring line area increases
Solution Approach 1:
The contact portion is locally widened only where needed for reliable contact with the bump, while the rest of the wiring line maintains a narrower width. This selective local quality enhancement improves contact stability without significantly increasing the overall wiring line area
Data Source
AI summary
Disclosed are semiconductor packages and package modules. The semiconductor package may include a semiconductor chip including an active surface having first to fourth lateral sides, a film substrate including a chip region and an edge region, a first wiring line on the chip and edge regions, and a first bump between the first wiring line and the active surface. The first bump may be adjacent the first lateral side. The first wiring line may include a contact portion in contact with the first bump. The contact portion may include a first and a second portion that is further away than the first portion from the first lateral side. A width of the second portion may be greater than that of the first portion. The first wiring line may vertically overlap the first lateral side and one of the second, third, and fourth lateral sides.