COF Package Closed-Loop Wiring for Stable Thin Display Bonding
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Solution Overview
Problem
Current Chip on Film (COF) packages face challenges in size, thickness, and production efficiency due to the need for multiple bonding processes and limited signal transmission stability, particularly when integrated with display and backlight boards.
Innovation Solution
The COF package design features a film substrate with a chip and outer leads arranged in multiple rows, utilizing a closed-loop wiring connection mode to increase signal paths and reduce thickness, allowing for single-layer or dual-layer conductive material usage, which enhances signal stability and reduces the number of packages required, thereby improving production efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional COF package design is used with multiple bonding processes, then signal transmission stability is improved, but production efficiency deteriorates and manufacturing complexity increases
Solution Approach 1:
The patent combines multiple bonding processes into a single bonding operation by integrating the COF package structure with direct mounting capabilities. The package design allows simultaneous bonding to both display panel and backlight board, reducing the number of separate bonding steps while maintaining signal transmission stability through the integrated structure.
Solution Approach 2:
The COF package is designed with multi-functional capabilities, serving both signal transmission and structural bonding functions simultaneously. The package structure can be universally applied to different mounting configurations (display panel, backlight board, or both), eliminating the need for specialized bonding processes for each application.
2Adaptability or versatility
If COF package size and thickness are reduced to meet display device requirements, then adaptability is improved, but signal transmission stability deteriorates
Solution Approach 1:
The patent transitions from traditional planar lead arrangements to a three-dimensional stacked configuration with multiple lead rows (first row, second row, third row) at different positions. This dimensional reorganization allows compact packaging while maintaining adequate signal paths through vertical and lateral routing, preventing signal degradation despite reduced overall package size.
Solution Approach 2:
The package design nests multiple functional elements within a compact structure, with inner leads positioned between outer leads, and multiple lead rows arranged in nested configurations. This nesting approach maximizes space utilization, allowing stable signal transmission paths to be maintained within a reduced package footprint.
3Area of stationary object
If multiple rows of outer leads are arranged closely to reduce package size, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the outer leads into multiple distinct rows (first row, second row, third row) with clear spatial separation and defined positioning relationships. Each row is independently configured with specific pitch and spacing parameters, allowing manufacturing processes to target each row separately and maintain precision without requiring ultra-fine overall packaging tolerance.
Data Source
AI summary
A Chip on Film (COF) package and a display device including the same are provided. The COF package includes: a film substrate; a chip arranged within a chip region on the film substrate; outer leads; and inner leads. The outer leads are arranged on the same side of the chip region and arranged as at least two rows of outer leads. The inner leads are arranged on a first side and a second side of the chip and connected with the chip. The at least two rows of outer leads include a first row and a second row of outer leads, the first row of outer leads are between the second row of outer leads and the chip, and wirings between at least part of leads among the second row of outer leads and the inner leads on the second side of the chip adopt a closed-loop like connection mode.