Selective Coherence Directory Controller for Multiprocessor Systems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Hardware coherence mechanisms in shared memory multiprocessing systems are complex and costly to implement, and deterministic coherence mechanisms can lead to performance issues, especially for heavily shared coherence units.
Innovation Solution
A coherence directory and controller system that selectively initiates coherence activity for subsequent requests based on the type of the request and the completion status of previous requests, allowing parallel coherence activity for simpler cases while blocking more complex cases until previous requests are completed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deterministic coherence mechanisms block subsequent requests until previous requests complete, then coherence correctness is ensured, but performance suffers especially for heavily shared coherence units
Solution Approach 1:
The patent applies dynamics by making the coherence mechanism adaptive rather than static. The directory entry includes a field indicating whether parallel requests are permitted, allowing the system to dynamically switch between blocking and non-blocking behavior based on the specific coherence unit and access patterns. This resolves the contradiction by enabling high-performance parallel handling when safe, while maintaining correctness through selective blocking when necessary.
Solution Approach 2:
The patent applies local quality by treating different coherence units differently. Instead of a uniform blocking approach for all coherence units, each directory entry can independently specify whether parallel requests are permitted. This allows heavily shared coherence units to use blocking for correctness while less-contended units use parallel handling for performance, optimizing the system as a whole.
2Reliability
If hardware coherence mechanisms are implemented to ensure consistent memory updates, then coherence is maintained, but the mechanism becomes complex and expensive to implement and repair
Solution Approach 1:
The patent introduces a software-based coherence protocol as an intermediary layer between processors and memory. Instead of complex hardware coherence logic, the patent uses software agents that communicate with a directory structure to manage coherence. This software intermediary simplifies the hardware design while maintaining coherence correctness through protocol-based coordination.
Solution Approach 2:
The patent uses a directory structure that maintains copies of coherence state information for each coherence unit. The directory entries track which processors have copies of coherence units and their validity states, allowing the system to manage coherence through information copying and validation rather than complex hardware interlocks.
3Reliability
If directory entries block all subsequent requests until completion, then deterministic coherence is maintained, but latency increases for valid parallel requests
Solution Approach 1:
The patent makes the blocking behavior dynamic by including a permission field in each directory entry that indicates whether parallel requests are permitted. This allows the system to adaptively allow or block parallel requests based on the specific coherence unit's characteristics and current state, reducing unnecessary latency while maintaining deterministic coherence when required.
Solution Approach 2:
The patent changes the parameter of request handling from a fixed blocking mode to a variable mode controlled by the parallel request permission field in directory entries. This parameter change allows the system to optimize between deterministic blocking and performance-oriented parallel handling based on workload characteristics and coherence unit properties.
Data Source
AI summary
In one embodiment, a node for a multi-node computer system comprises a coherence directory and a coherence controller. The coherence directory comprises a plurality of entries, wherein each entry corresponds to a respective coherence unit and stores a state identifying which nodes in the computer system are storing a copy of the coherence unit and further identifying a coherence state of the coherence unit according to a coherence protocol implemented in the computer system. Coupled to the directory and coupled to receive a first request for a requested coherence unit having a first entry in the coherence directory, the coherence controller is coupled to receive a second request for the requested coherence unit. The coherence controller is configured to selectively initiate coherence activity for the second request, if coherence activity for the first request is not yet complete, dependent on a type of the second request.