On-Chip Coherence Domain Assignment for Cache Overhead Reduction
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Solution Overview
Problem
In data processing systems, maintaining cache coherence across multiple processing units and caches becomes cumbersome and inefficient, especially as the number of caches grows, leading to high overhead and unnecessary consistency requirements for applications that do not need it.
Innovation Solution
A method for assigning caches and memory to on-chip coherence domains, where cores and their caches are partitioned into domains, and memory is dynamically allocated based on application needs, using a mapping table to manage cache coherence and reduce unnecessary coherence domain overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherence is maintained across all processing units and caches, then data consistency is improved, but system overhead and complexity increase significantly
Solution Approach 1:
The patent divides the entire cache coherence domain into multiple sub-domains, where each sub-domain is assigned to a specific application or group of applications. This segmentation allows coherence to be maintained only within relevant sub-domains rather than across the entire system, reducing the overhead of coherence management while maintaining data consistency where needed.
Solution Approach 2:
The patent implements different coherence policies for different sub-domains based on application requirements. Not all processing units or caches need to maintain coherence with all other units. The system allows local coherence management within sub-domains while permitting non-coherent access across domain boundaries, optimizing the balance between consistency and overhead.
2Device complexity
If coherence domains are created to reduce overhead, then management complexity is improved, but data consistency may be compromised for applications that require it
Solution Approach 1:
The patent implements dynamic coherence domain assignment where domains can be created, merged, or split based on runtime application requirements. The system can adapt coherence domain boundaries dynamically to match actual memory access patterns and application needs, ensuring data consistency is maintained when required while minimizing overhead when not needed.
Solution Approach 2:
The patent allows changing coherence parameters such as domain granularity, assignment policies, and coherence protocols based on workload characteristics. The system can adjust these parameters dynamically to optimize between consistency and overhead for different application types.
3Device complexity
If fixed memory allocation to coherence domains is used, then mapping complexity is reduced, but adaptability to different application needs deteriorates
Solution Approach 1:
The patent implements dynamic memory allocation to coherence domains based on runtime application requirements. Instead of fixed pre-defined mappings, the system can allocate memory regions to specific domains dynamically, allowing flexible adaptation to different application memory access patterns and requirements.
Solution Approach 2:
The patent introduces a memory manager or mapper as an intermediary component that translates between physical memory addresses and coherence domain assignments. This intermediary layer enables flexible, dynamic memory-to-domain mapping without increasing the complexity at the hardware coherence management level.
Data Source
AI summary
A mechanism for assigning memory to on-chip cache coherence domains assigns caches within a processing unit to coherence domains. The mechanism assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller.