Coherence Interconnect Device for Real-Time Kernel Code Tracking

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Solution Overview

Problem

Existing systems lack an efficient method to track and modify kernel code pages in real-time without terminating the execution of the code, which is essential for live patching and code profiling in virtualized computer systems.

Innovation Solution

A device connected via a coherence interconnect to processors stores kernel code pages in local memory and monitors cache-line accesses, allowing for real-time updates and tracking of code execution, enabling the return of modified code portions instead of the original cache lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If code pages are stored in local memory of a device connected via coherence interconnect, then real-time tracking and modification of kernel code is enabled, but system complexity increases

Engineering Contradiction:
Improvereal-time code tracking capabilityVSAvoidsystem architecture complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The device connected via coherence interconnect acts as an intermediary between the processors and the code pages stored in local memory. This intermediary monitors cache-line accesses to code pages and enables real-time tracking and modification of kernel code without requiring direct complex interactions between processors and memory systems, thus achieving reliable real-time tracking while managing system complexity through the intermediary component

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If modified code portions are returned instead of original cache lines, then live patching capability is improved, but code execution integrity risks increase

Engineering Contradiction:
Improvelive patching capabilityVSAvoidcode execution integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system implements feedback mechanisms where the device monitors cache-line accesses to code pages, tracks which code portions are being executed, and provides information about the code execution state. This feedback loop enables live patching by allowing modified code portions to be returned while maintaining awareness of code execution integrity through continuous monitoring and tracking of cache-line accesses

Inventive Principle:
Principle #23Feedback

3Measurement precision

If coherence interconnect monitoring is used to track cache-line accesses, then code coverage measurement is improved, but processing overhead increases

Engineering Contradiction:
Improvecode coverage measurement accuracyVSAvoidprocessing overhead
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The coherence interconnect monitoring leverages the existing coherence protocol traffic generated by normal code execution to track cache-line accesses. Instead of requiring separate dedicated monitoring mechanisms, the system uses the self-generated coherence traffic from processor-memory interactions to automatically track which code pages are being accessed and executed, thereby achieving precise code coverage measurement while minimizing additional processing overhead by repurposing existing system traffic

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12008361B2Coherence-based dynamic code rewriting, tracing and code coverage
Publication Date: 2024.06.11 VMWARE INC
  • US12008361B2 patent drawing
  • US12008361B2 patent drawing
  • US12008361B2 patent drawing

AI summary

A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.