Coherence Manager for Multiprocessor Cache Maintenance
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Solution Overview
Problem
In multiprocessor systems, maintaining cache coherence across multiple processors is inefficient, consuming power, processing cycles, and bandwidth, and complicates software development due to the disparity between microprocessor clock speeds and memory access times.
Innovation Solution
A method and processor core design that utilize a coherence manager to detect and propagate cache maintenance operations within coherent domains, ensuring cache coherence by sending coherent requests and messages between processors, thereby reducing the burden on software developers and optimizing power and bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cache maintenance operations are used in multiprocessor systems, then cache coherence can be maintained, but power consumption increases
Solution Approach 1:
The patent extracts the cache coherence management function from individual processor cache maintenance operations and centralizes it in a coherence manager. The coherence manager receives coherence requests from processors, determines the appropriate coherent domain, and distributes targeted invalidation messages only to processors within that domain, rather than broadcasting to all processors. This extraction and centralization reduces unnecessary power consumption from widespread cache maintenance operations.
Solution Approach 2:
The patent segments the multiprocessor system into multiple coherent domains, where each domain is a subset of processors that share cache coherence requirements. By segmenting the system, invalidation messages are restricted to specific domains rather than being propagated system-wide. This segmentation reduces the number of processors that need to respond to each coherence request, thereby reducing overall power consumption while maintaining coherence within each segment.
2Reliability
If traditional cache maintenance operations are used in multiprocessor systems, then cache coherence can be maintained, but processing cycles are consumed
Solution Approach 1:
The coherence manager acts as an intermediary between processors and the cache coherence mechanism. Instead of processors directly performing cache maintenance operations on all other processors, they send requests to the coherence manager, which then handles the distribution of invalidation messages. This intermediary approach streamlines the coherence management process, reduces the processing cycle overhead for individual processors, and enables more efficient parallel operation of multiple processors.
Solution Approach 2:
The coherence manager performs preliminary actions by determining the appropriate coherent domain before distributing invalidation messages. By pre-determining which processors belong to the relevant coherent domain and preparing the targeted message distribution in advance, the system avoids unnecessary processing cycles that would be spent on system-wide broadcasts or trial-and-error coherence protocols.
3Reliability
If traditional cache maintenance operations are used in multiprocessor systems, then cache coherence can be maintained, but bandwidth consumption increases
Solution Approach 1:
The patent applies local quality by making cache coherence management localized to specific coherent domains rather than applying a uniform system-wide approach. Each coherent domain has its own subset of processors that share coherence requirements, and invalidation messages are tailored and directed specifically to those local processors. This localization reduces the bandwidth consumption associated with broadcasting coherence messages across the entire multiprocessor system.
4Reliability
If traditional cache maintenance operations are used in multiprocessor systems, then cache coherence can be maintained, but software complexity increases
Solution Approach 1:
The coherence manager provides self-service by autonomously determining coherent domains, routing coherence requests to the appropriate domains, and distributing invalidation messages without requiring software intervention. This self-service mechanism abstracts the complexity of cache coherence management from software, allowing developers to write simpler code without manually managing coherence protocols across multiple processors and domains.
Data Source
AI summary
A multiprocessor system maintains cache coherence among processors in a coherent domain. Within the coherent domain, a first processor can receive a command to perform a cache maintenance operation. The first processor can determine whether the cache maintenance operation is a coherent operation. For coherent operations, the first processor sends a coherent request message for distribution to other processors in the coherent domain and can cancel execution of the cache maintenance operation pending receipt of intervention messages corresponding to the coherent request. The intervention messages can reflect a global ordering of coherence traffic in the multiprocessor system and can include instructions for maintaining a data cache and an instruction cache of the first processor. Cache maintenance operations that are determined to be non-coherent can be executed at the first processor without sending the coherent request.