Multiple Coherence Planes for Distributed Memory Systems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Chip multithreading (CMT) systems face performance issues due to excessive memory access bandwidth requirements and latency on standard interconnects, such as multidrop buses and point-to-point interfaces, which are inadequate for maintaining coherency across multiple threads accessing shared memory locations.
Innovation Solution
The implementation of a distributed memory system with multiple coherence planes, where each coherence unit manages coherency independently and maps addresses to specific coherence planes, allowing for independent coherency activity and scalable bandwidth management, enabling efficient memory access and coherency maintenance across nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chip multithreading is implemented to utilize more transistors and increase processing capacity, then the processing throughput and resource utilization are improved, but the memory access bandwidth requirement and coherency maintenance complexity increase beyond the capability of standard interconnects
Solution Approach 1:
The patent divides the address space into multiple coherence planes, where each plane is independently managed by a separate coherence unit. This segmentation allows parallel processing of coherence requests across different planes, effectively increasing the memory access bandwidth capability without requiring a complete overhaul of the interconnect infrastructure. Each coherence unit can handle coherency operations for its assigned plane independently, enabling scalable bandwidth management for multithreaded workloads.
2Productivity
If multiple threads access shared memory locations concurrently, then the computational efficiency and resource utilization are improved, but the latency for maintaining coherency increases due to insufficient interconnect bandwidth
Solution Approach 1:
By segmenting the coherence management into multiple independent planes handled by separate coherence units, the system can process coherency operations in parallel. This reduces the latency for maintaining coherency across multiple threads because multiple coherence requests can be handled simultaneously across different planes rather than serially through a single coherence interface.
Solution Approach 2:
The patent introduces an additional dimension of parallelism by creating multiple coherence planes. Instead of having a single coherence management dimension, the system now operates across multiple dimensional planes, each independently managed. This dimensional expansion allows concurrent coherency operations to proceed in parallel, reducing overall latency while maintaining computational efficiency.
3Device complexity
If a single coherence interface is used to manage coherency for all threads, then the device complexity is kept low, but the bandwidth and latency performance become insufficient for multithreaded workloads
Solution Approach 1:
The patent segments the coherence management function into multiple independent coherence units, each responsible for a specific coherence plane. This segmentation increases the available bandwidth for coherency operations while keeping each individual coherence unit relatively simple. The modular structure allows the system to scale bandwidth by adding more planes and units without creating a single complex coherence management structure.
Data Source
AI summary
In one embodiment, a node comprises at least one processor core and a plurality of coherence units. The processor core is configured to generate an address to access a memory location. The address maps to a first coherence plane of a plurality of coherence planes. Coherence activity is performed within each coherence plane independent of other coherence planes, and a mapping of the address space to the coherence planes is independent of a physical location of the addressed memory in a distributed system memory. Each coherence unit corresponds to a respective coherence plane and is configured to manage coherency for the node and for the respective coherence plane. The coherence units operate independent of each other, and a first coherence unit corresponding to the first coherence plane is coupled to receive the address if external coherency activity is needed to complete the access to the memory location.