Coherence Switch for I/O Traffic Routing
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Solution Overview
Problem
Systems on chips face high costs, performance, and power consumption due to the need to check every transaction for cache coherency, with I/O device traffic competing for memory bandwidth and causing unnecessary snoop activity.
Innovation Solution
A coherence switch that routes transactions through two separate paths, one for coherent and one for non-coherent traffic, using a configuration register with a software-writeable and hardware-controlled shadow copy to dynamically reallocate traffic based on transaction identifiers, allowing software to initiate changes in routing without disrupting system behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If every transaction from I/O devices is checked for cache coherency, then coherency is maintained, but hardware cost, performance, and power consumption increase
Solution Approach 1:
The patent segments transactions into two distinct categories: coherent transactions and non-coherent transactions. A segmentation mechanism identifies and separates these transaction types, routing them through different paths in the interconnect network. This allows coherent transactions to undergo full coherency checking while non-coherent transactions bypass this overhead, resolving the contradiction between maintaining coherency and reducing hardware complexity.
Solution Approach 2:
The patent introduces an intermediary mechanism (coherency checking logic or snoop filter) that selectively processes only coherent transactions. This intermediary acts as a gatekeeper, allowing non-coherent transactions to pass through without triggering expensive coherency checks. By mediating between the I/O devices and the cache system, it maintains coherency where needed while eliminating unnecessary overhead elsewhere.
2Reliability
If every transaction is checked for cache coherency, then coherency is maintained, but performance deteriorates
Solution Approach 1:
By segmenting transactions into coherent and non-coherent categories, the system applies coherency checking only where necessary. This selective approach maintains coherency reliability for relevant transactions while dramatically improving overall system performance by eliminating redundant checking operations on non-coherent transactions that would otherwise bottleneck the system.
Solution Approach 2:
The patent applies partial action by performing coherency checking only on a subset of transactions (coherent ones) rather than all transactions. This partial application of the coherency protocol maintains system correctness where needed while avoiding the performance penalty of applying it excessively to all traffic, thereby resolving the contradiction between reliability and productivity.
3Reliability
If every transaction is checked for cache coherency, then coherency is maintained, but power consumption increases
Solution Approach 1:
The segmentation of transactions into coherent and non-coherent types enables the system to activate power-intensive coherency checking logic only when processing coherent transactions. For non-coherent transactions, the system skips these expensive operations, thereby maintaining coherency reliability for necessary operations while significantly reducing overall power consumption across the system.
Solution Approach 2:
By applying coherency checking partially (only to coherent transactions) rather than excessively (to all transactions), the system maintains the necessary reliability guarantee while avoiding the unnecessary power consumption that would result from universal checking. This selective application directly addresses the contradiction between maintaining coherency and minimizing energy use.
4Ease of operation
If I/O device traffic is routed through the processor complex, then memory access is enabled, but memory bandwidth is competed for and snoop activity increases
Solution Approach 1:
The patent segments the memory access path into two separate routes: one for coherent transactions that must pass through the processor complex to enable proper cache coherency handling, and another for non-coherent transactions that can take a direct path to memory. This segmentation allows memory access to remain easy for all devices while preventing non-coherent I/O traffic from competing for bandwidth or generating unnecessary snoop activity in the processor complex.
Solution Approach 2:
The patent introduces an intermediary routing mechanism (coherence switch or router) that directs transactions to appropriate paths based on their coherency requirements. This intermediary enables memory access for all I/O devices while intelligently routing non-coherent traffic away from the processor complex, thereby eliminating unnecessary bandwidth competition and snoop activity while preserving easy memory access capability.
Data Source
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AI summary
A system, apparatus, and method for routing traffic in a SoC from I/O devices to memory. A coherence switch routes coherent traffic through a coherency port on a processor complex to a real-time port of a memory controller. The coherence switch routes non-coherent traffic to a non-real time port of the memory controller. The coherence switch can also dynamically switch traffic between the two paths. The routing of traffic can be configured via a configuration register, and while software can initiate an update to the configuration register, the actual coherence switch hardware will implement the update. Software can write to a software-writeable copy of the configuration register to initiate an update to the flow path to memory for a transaction identifier. The coherence switch detects the update to the software-writeable copy, and then the coherence switch updates the working copy of the configuration register and implements the new routing.