Coherency Adapter XTAG DMA Translation
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Solution Overview
Problem
Current computer systems face inefficiencies in direct memory access (DMA) between accelerators and processors due to the need for coherency-based operations, which introduce additional latency and data size limitations, and require translation control entries and pinned pages.
Innovation Solution
The implementation of a coherency adapter that uses translation tags (XTAGs) to facilitate DMA operations directly, eliminating the need for coherency-based operations and allowing DMA requests to be serviced without additional packet headers or pinned pages, thereby improving bandwidth and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coherency-based operations are used for DMA between accelerator and processor, then data consistency is maintained, but additional latency is introduced
Solution Approach 1:
The coherency adapter acts as an intermediary device between the accelerator and the memory system. It intercepts DMA requests from the accelerator, performs address translation using translation tags (XTAGs), and manages coherency protocols independently. This mediator approach allows the accelerator to issue simple DMA requests without implementing complex coherency logic, while the adapter handles the coherency maintenance in the background, reducing the latency impact on the critical DMA path.
2Adaptability or versatility
If translation control entries and pinned pages are required for DMA operations, then address translation is enabled, but device complexity and memory management overhead increase
Solution Approach 1:
The patent extracts the address translation functionality from the traditional memory management unit (MMU) path and implements it directly in the coherency adapter using translation tags (XTAGs). The XTAGs are stored in a dedicated translation buffer within the adapter, allowing address translation to occur locally at the DMA request point rather than requiring full translation control entries in the MMU. This extraction simplifies the DMA operation by providing a lightweight, dedicated translation mechanism that doesn't require the full overhead of pinned pages or complex translation control structures.
3Ease of manufacture
If cache line limitations are imposed on DMA transfers, then memory alignment is simplified, but transmission size is restricted
Solution Approach 1:
The patent introduces a new dimension to address translation by implementing granular XTAG-based translation that operates at the byte or word level rather than being constrained to cache line boundaries. The translation buffer in the coherency adapter maintains mapping information that can be accessed at any address boundary, allowing DMA transfers to span arbitrary memory regions without being forced into cache line-aligned segments. This dimensional change in the translation mechanism enables large, contiguous DMA transfers while maintaining the simplicity of address mapping.
Data Source
AI summary
Direct memory access between an accelerator and a processor using a coherency adapter including receiving, by the adapter from the accelerator, a request to initiate a DMA transfer; providing, by the adapter, a translation tag (‘XTAG’) to the accelerator; receiving, by the adapter from the accelerator, a DMA instruction comprising the XTAG; generating, by the adapter, a DMA instruction comprising a real address based on the XTAG; and sending, by the adapter, the generated DMA instruction comprising the real address to a communications bus.