Coherency Control Message Flow via Ordered Interconnect Channels
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Solution Overview
Problem
Existing data processing systems face complexity and performance issues in managing coherence across multiple data copies due to the need for additional overhead and circuit area in protocols like the ACE protocol, which do not easily scale with system size.
Innovation Solution
The system employs a configuration where eviction and read messages are sent on the same communication channel, ensuring the eviction message is processed ahead of the read message, eliminating the need for acknowledgement waiting and reducing overhead, with interconnect circuitry preventing message reordering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If protocol-driven coherency control is used (e.g., ACE protocol), then proper coherence is ensured, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the coherency control logic from the agents and places it in a dedicated coherency control circuitry. The agents only need to send simple evict messages and read messages through the interconnect, while the complex coherence management is handled externally by the coherency control circuitry, reducing the complexity burden on individual agents.
Solution Approach 2:
The interconnect circuitry acts as an intermediary that provides ordered communication channels between agents and coherency control circuitry. By guaranteeing message ordering through the interconnect's communication channels, the system achieves reliable coherency control without requiring complex protocol implementation within each agent.
2Reliability
If protocol-driven coherency control is used, then proper coherence is ensured, but power consumption increases
Solution Approach 1:
By extracting complex coherency control logic from individual agents to dedicated coherency control circuitry, the patent reduces the operational complexity and power consumption of each agent. The agents only perform simple message sending operations rather than full protocol compliance, significantly reducing their power requirements.
3Reliability
If protocol constraints are enforced, then coherence is maintained, but performance slows down
Solution Approach 1:
The interconnect circuitry is configured in advance to guarantee that evict messages are delivered before read messages through ordered communication channels. This preliminary ordering arrangement eliminates the need for agents to stall and wait for acknowledgments, as the ordering is guaranteed by the interconnect's channel configuration rather than protocol enforcement.
Solution Approach 2:
The communication channels themselves provide the ordering service through their physical or logical configuration, rather than requiring active protocol enforcement. The channels inherently prevent read messages from overtaking evict messages, making the ordering service self-providing and eliminating performance-stalling acknowledgment waits.
4Quantity of substance
If system size grows, then processing capacity increases, but protocol compliance becomes more difficult
Solution Approach 1:
The patent segments the coherency control function from the data processing agents, placing it in dedicated coherency control circuitry. This segmentation allows the system to scale in size by adding more agents without increasing the protocol compliance complexity of each individual agent, as they all use the same simplified message-sending interface.
Solution Approach 2:
The interconnect circuitry provides a universal ordered communication interface that serves all agents regardless of system size. The same communication channel ordering mechanism works for any number of agents, making the system scalable without increasing individual agent complexity.
Data Source
AI summary
A coherent memory system includes a plurality of level 1 cache memories 6 connected via interconnect circuitry 18 to a level 2 cache memory 8. Coherency control circuitry 10 manages coherency between lines of data. Evict messages from the level 1 cache memories to the coherency control circuitry 10 are sent via the read address channel AR. Read messages are also sent via the read address channel AR. The read address channel AR is configured such that a read message may not be reordered relative to an evict message. The coherency control circuitry 10 is configured such that a read message will not be processed ahead of an evict message. The level 1 cache memories 6 do not track in-flight evict messages. No acknowledgement of an evict message is sent from the coherency control circuitry 10 back to the level 1 cache memory 6.