Coherency Control Module for Interrupt Notification Validation
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Solution Overview
Problem
Existing systems fail to ensure that a CPU is notified about data being written to a shared memory only after the writing instruction is completed, leading to potential execution of instructions on data not yet stored, which can cause data coherency issues.
Innovation Solution
A coherency control module that suspends the interrupt notification until the writing instruction is completed, with verification methods including read after write or emptying buffers by writing data equal to their size, allowing for efficient validation of write operations across multiple modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If modules issue interrupt requests immediately after issuing write instructions to notify the CPU, then the CPU can be notified promptly about data transfers, but the CPU may execute instructions on data that has not yet been stored in memory
Solution Approach 1:
The patent applies preliminary action by having the coherency control module suspend interrupt requests until the write operation is fully completed and verified. The module performs the write instruction, then executes a verification step (either reading back the data or checking buffer status) before allowing the interrupt to proceed. This ensures data is actually in memory before the CPU is notified, preventing execution on unstored data while maintaining timely interrupt notification.
2Reliability
If a read instruction is performed after every write instruction to verify data completion, then data coherency is ensured, but system performance deteriorates due to the lower priority of read instructions
Solution Approach 1:
The patent merges the verification process into the interrupt handling mechanism itself. Instead of performing separate read-after-write operations for every data transfer, the coherency control module integrates verification (through buffer status checking or selective read operations) into the interrupt request flow. Multiple interrupt requests can be batched and verified together, reducing the overhead compared to individual verification operations.
Solution Approach 2:
The coherency control module acts as an intermediary between the modules and the CPU. It intercepts interrupt requests, performs the necessary verification of write completion through buffer status checks or coordinated read operations, and then forwards verified interrupts to the CPU. This intermediary approach centralizes the verification logic and reduces the performance impact compared to distributed read-after-write operations at each module.
3Reliability
If memory lines are monitored to verify write completion, then data coherency can be ensured, but the system becomes cumbersome and expensive due to the large number of lines required
Solution Approach 1:
The patent extracts the coherency verification function from the physical memory lines themselves. Instead of monitoring individual data lines to detect write completion, the system uses a separate control mechanism where the coherency control module manages verification through buffer status registers or control signals. This separates the verification function from the data path, avoiding the need for extensive monitoring of memory lines.
Solution Approach 2:
The coherency control module serves as an intermediary that manages write verification without requiring direct monitoring of memory data lines. It uses buffer status indicators and control signals to track write completion, replacing the need for complex line-monitoring circuitry with a more manageable control-plane approach.
Data Source
AI summary
The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a CPU; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request notifying a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus; suspending the interrupt request; validating a completion of an execution of the writing instruction; wherein the validating is performed after the suspending; and resuming the interrupt request after the completion of the execution of the writing is validated, whereby to notify a to the CPU about the completion of the execution of the writing instruction.