Coherency Controller for Divided L2 Cache Latency Reduction
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Solution Overview
Problem
In directory-based ccNUMA multiprocessor systems with a divided cache configuration, maintaining coherency during block type changes is challenging due to increased latency and bus occupation ratios, especially when the number of cores increases, leading to inefficiencies in data transfer and state switching between CPUs.
Innovation Solution
The implementation of a coherency controller that manages L2 cache memories across multiple processor cores, utilizing a flag for exclusive right acquisition responses to ensure data integrity and coherence without significant changes to inter-CPU control methods, allowing for efficient data transfer and state management within a divided cache configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a divided cache configuration is used in directory-based ccNUMA multiprocessor systems, then cache capacity and core integration are improved, but latency and bus occupation ratios increase during coherency control
Solution Approach 1:
The cache system is divided into multiple L2 cache memories, each associated with specific processor cores. This segmentation allows parallel coherency control operations to occur in different cache memories simultaneously, reducing overall latency while maintaining total cache capacity.
Solution Approach 2:
A coherency controller is introduced as an intermediary component that manages coherency control between L2 cache memories. The controller receives coherency control requests, determines target L2 cache memories, and routes requests appropriately, thereby reducing bus occupation ratios and latency through intelligent request management.
2Productivity
If the number of processor cores is increased in a divided cache configuration, then processing power is improved, but coherency maintenance becomes more complex and time-consuming
Solution Approach 1:
The system segments coherency control by associating specific L2 cache memories with specific processor cores. This segmentation allows independent coherency management for each cache-core group, reducing overall control complexity while supporting increased core counts.
Solution Approach 2:
L2 cache memories are pre-associated with processor cores and pre-configured to handle coherency control requests. This preliminary organization enables direct routing of coherency requests without complex dynamic decision-making, simplifying control as core numbers increase.
3Reliability
If coherency control requests are routed through the inter-CPU bus in a divided cache system, then data coherence is maintained, but bus occupation ratios increase and performance degrades
Solution Approach 1:
The coherency controller acts as an intermediary that receives coherency control requests and determines whether targets are local L2 cache memories. When targets are local, the controller routes requests directly to the appropriate L2 cache memory, bypassing the inter-CPU bus and reducing bus occupation ratios while maintaining coherence.
Solution Approach 2:
Coherency control traffic is segmented into local L2 cache memory requests and inter-CPU bus requests. By routing local requests directly to segmented L2 cache memories, the system reduces inter-CPU bus occupation ratios while maintaining data coherence through dedicated local pathways.
Data Source
AI summary
An operation processing apparatus includes: processor cores configured to perform an operation processing; cache memories each provided for the respective processor cores; and a controller configured to perform a coherency control between the cache memories, wherein, the controller, in the coherency control, in a case where one or more shared cache memories which share a target data block for a store request are present in the cache memories when the store request is received from a request cache memory included in the cache memories: controls one cache memory of the one or more shared cache memories such that the target data block is transferred to the request cache memory; receives an exclusive right acquisition response from another operation processing apparatus which manages a state of the target data block; and transmits the exclusive right acquisition response to the request cache memory.