Coherency Controller Trace Condensation for Multi-Processor Debugging

Solution Overview

Problem

Current PDTrace technology is limited to single-processor systems and faces challenges in efficiently processing and correlating trace information from multi-processor systems, resulting in information overload and long processing times due to high overhead techniques like time stamps.

Innovation Solution

A system that includes a coherence manager and a computer-readable storage medium with executable instructions to characterize a coherency controller, which receives processor trace information, generates condensed coherence indicators, and produces trace streams with trace metrics, allowing for efficient correlation and debugging of multi-processor systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If time stamps or high overhead techniques are used to organize trace information from multiple processors, then trace information can be organized and correlated, but information bandwidth increases and processing times increase

Engineering Contradiction:

Improvetrace information organizationVSAvoidinformation bandwidth

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential correlation information needed for multi-processor trace analysis by using condensed coherence indicators that identify cache coherence events without including full time stamp data for every trace event. This selective extraction reduces information bandwidth while maintaining the ability to organize and correlate trace information across multiple processors.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of adding overhead information (time stamps) to every trace event to enable correlation, the patent inverts the approach by using condensed coherence indicators that are generated by the coherence manager based on cache coherence events. This inversion reduces the amount of information that needs to be processed while still enabling effective trace organization.

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If time stamps or high overhead techniques are used to organize trace information from multiple processors, then trace information can be organized and correlated, but processing times increase

Engineering Contradiction:

Improvetrace information organizationVSAvoidprocessing times

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts only the essential correlation information needed for multi-processor trace analysis by using condensed coherence indicators that identify cache coherence events without including full time stamp data for every trace event. This selective extraction reduces information bandwidth while maintaining the ability to organize and correlate trace information across multiple processors.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of adding overhead information (time stamps) to every trace event to enable correlation, the patent inverts the approach by using condensed coherence indicators that are generated by the coherence manager based on cache coherence events. This inversion reduces the amount of information that needs to be processed while still enabling effective trace organization.

Inventive Principle:

Principle #13The other way round (Inversion)

3Productivity

If condensed coherence indicators are used to reduce information bandwidth, then processing efficiency improves, but trace information may become less detailed

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidtrace information detail

Core Design Contradiction:

ProductivityVSLoss of information

Solution Approach 1:

The patent changes the parameter of trace information representation by using condensed coherence indicators that capture essential cache coherence events in a compressed format. The coherence manager generates these indicators based on actual coherence events (such as cache line invalidations, shared state transitions), ensuring that critical debugging information is preserved while reducing overall data volume for more efficient processing.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8230202B2Apparatus and method for condensing trace information in a multi-processor system

Publication Date: 2012.07.24 ARM FINANCE OVERSEAS LTD

AI summary

A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a condensed coherence indicator. Circuitry produces a trace stream with trace metrics and condensed coherence indicators.