Coherency Directory Cache Block Request Grouping
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Solution Overview
Problem
In symmetric multiprocessing (SMP) systems, the latency and bandwidth consumption in memory access can be high due to the limited link bandwidth between node controllers, which hinders efficient data retrieval and processing across multiple processor nodes.
Innovation Solution
Implementing a coherency directory cache with a TCAM (Ternary Content Addressable Memory) to manage cache coherency and group multiple cache line requests with similar state and ownership characteristics, allowing for speculative retrieval and reduced bandwidth usage through block request grouping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple individual cache line requests are sent separately, then cache coherency can be maintained, but latency increases and bandwidth consumption increases
Solution Approach 1:
The patent groups multiple individual cache line requests into a single block request when the requests share the same state and ownership characteristics. This merging reduces the number of separate transactions on the interconnect, thereby reducing latency and bandwidth consumption while maintaining cache coherency through the directory-based validation mechanism.
Solution Approach 2:
The system performs preliminary grouping of cache line requests based on their state and ownership information stored in the coherency directory before sending requests to the interconnect. This preliminary action identifies opportunities to batch requests together, reducing the total number of transactions needed while ensuring coherency requirements are met.
2Reliability
If multiple individual cache line requests are sent separately, then cache coherency can be maintained, but bandwidth consumption increases
Solution Approach 1:
The patent merges multiple individual cache line requests into a single block request when they share the same state and ownership characteristics. This reduces the total number of transactions on the interconnect, thereby reducing bandwidth consumption and energy usage while maintaining cache coherency through directory-based validation.
3Loss of time
If block request grouping is implemented, then latency is reduced and bandwidth efficiency is improved, but device complexity increases
Solution Approach 1:
The patent introduces a coherency directory cache as an intermediary structure between the cache and the interconnect. This intermediary stores state and ownership information that enables intelligent grouping of requests, reducing latency and bandwidth consumption while centralizing the complexity management in a dedicated structure rather than分散 throughout the system.
Data Source
AI summary
To reduce latency and bandwidth consumption in systems, systems and methods are provided for grouping multiple cache line request messages in a related and speculative manner. That is, multiple cache lines are likely to have the same state and ownership characteristics, and therefore, requests for multiple cache lines can be grouped. Information received in response can be directed to the requesting processor socket, and those speculatively received (not actually requested, but likely to be requested) can be maintained in queue or other memory until a request is received for that information, or until discarded to free up tracking space for new requests.