Coherency Interconnect Multiprocessor Messaging
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Solution Overview
Problem
In multiprocessor systems, dedicated interprocessor messaging interconnects face inefficiencies due to complex message routing and security vulnerabilities, requiring extensive memory accesses and relying on generic messages that can be exploited for unauthorized access.
Innovation Solution
A shared coherency interconnect is used to transmit both coherency and interprocessor messages using a dual-mode message format, allowing processors to determine message type and handle accordingly, reducing memory look-ups and enhancing security through message filtering and encryption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated interprocessor messaging interconnect is used, then message transmission between processors is enabled, but the system complexity increases and security vulnerabilities arise due to generic message formats
Solution Approach 1:
The patent combines the dedicated interprocessor messaging interconnect with the existing coherency interconnect into a single shared interconnect. This merging eliminates the need for separate messaging hardware, reducing system complexity while maintaining message transmission capabilities through the unified interconnect structure.
Solution Approach 2:
The shared interconnect is designed to handle multiple message types (coherency messages, interprocessor messages, and security messages) through a universal message format. This multi-functionality allows a single interconnect to replace multiple dedicated interconnects, reducing overall system complexity.
2Reliability
If a dedicated interprocessor messaging interconnect is used, then interprocessor communication is achieved, but security breaches can occur due to reliance on generic messages
Solution Approach 1:
The patent applies different security measures to different message types within the shared interconnect. Security-critical messages (such as those to security devices) use encrypted formats with authentication, while other messages use standard formats. This localized security approach protects vulnerable communication paths without compromising overall system performance.
Solution Approach 2:
The patent introduces message filtering and validation mechanisms as intermediaries between the shared interconnect and target processors/security devices. These intermediaries verify message authenticity and routing information, preventing unauthorized access while allowing legitimate communication to proceed efficiently.
3Ease of operation
If routing tables are configured during start-up, then message routing is established, but memory bandwidth is reduced due to extensive memory accesses
Solution Approach 1:
The patent performs routing table configuration and population during system start-up or initialization phases, before normal operation begins. This preliminary action ensures that routing information is pre-loaded into the interconnect, eliminating the need for frequent memory accesses during runtime and preserving memory bandwidth for actual data processing.
Solution Approach 2:
The shared interconnect incorporates automatic routing determination capabilities that use the pre-configured routing tables to quickly identify destination processors without requiring extensive memory lookups during message transmission. This self-service routing reduces memory access overhead and improves overall system productivity.
Data Source
AI summary
A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.