Coherency Locking Schemes for Memory Sub-Systems
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Solution Overview
Problem
Traditional coherency operations in memory sub-systems result in increased processing overhead and latency due to the need for constant locking, unlocking, and checking of coherency during write operations, including those initiated for media management like garbage collection.
Innovation Solution
Implementing coherency locking schemes where coherency operations are performed only for write commands received from a host system, skipping these operations for internal writes such as those during garbage collection, and using a hardware coherency block to manage coherency locks and releases, allowing multiple processing cores to perform independent operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coherency operations are performed for all write commands (including internal writes), then data coherency is maintained, but processing overhead and latency increase
Solution Approach 1:
The patent segments write commands into two categories: host-initiated write commands and internal write commands (such as garbage collection operations). Different coherency handling strategies are applied to each segment: host writes trigger coherency lock operations to ensure data integrity, while internal writes skip coherency operations to reduce overhead. This segmentation resolves the contradiction by applying coherency checks only where necessary for external data consistency.
Solution Approach 2:
The patent applies partial coherency operations by performing coherency lock and unlock operations only for host-initiated write commands, rather than for all write commands. This partial action approach maintains data coherency for external operations while avoiding unnecessary coherency management for internal operations, thereby reducing processing overhead and latency without compromising essential data integrity.
2Reliability
If coherency locking operations are performed for every write command, then data integrity is ensured, but processing overhead increases
Solution Approach 1:
The patent divides write command handling into distinct segments based on command origin. Host write commands undergo full coherency management (lock, update mapping, unlock), while internal write commands bypass coherency operations. This segmentation reduces processing overhead by eliminating redundant coherency checks for internal operations while maintaining data integrity for external operations.
Solution Approach 2:
The patent extracts coherency management operations from the universal write command processing path and applies them selectively only to host-initiated commands. By taking out the coherency lock/unlock operations from the general write path and applying them only where needed (host writes), the system reduces processing overhead while maintaining data integrity for external operations.
3Reliability
If multiple processing cores perform coherency operations, then coherency management is comprehensive, but message exchange and coordination overhead increase
Solution Approach 1:
The patent implements a self-service coherency management model where each processing core independently tracks and manages its own coherency state through local coherency counters. Cores increment counters when acquiring coherency locks and decrement them when releasing locks, eliminating the need for inter-core message exchange or centralized coordination. This self-service approach maintains comprehensive coherency management across multiple cores while significantly reducing coordination overhead.
Data Source
AI summary
Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.