Coherent Attached Processor Proxy for Cache Coherency

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Solution Overview

Problem

In distributed shared memory computer systems, attached processors often face challenges in participating in system-wide coherency responses due to insufficient speed, bandwidth, and reliability of communication links, which can lead to delays in cache coherency protocols, affecting the timely access and synchronization of memory blocks across multiple processor cores.

Innovation Solution

A coherent attached processor proxy (CAPP) is introduced to participate on behalf of the attached processor in determining system-wide coherency responses, ensuring compliance with the timing requirements of the cache coherency protocol by managing memory access requests and translating system-wide combined responses into internal actions, allowing for programmable support of various attached processors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If attached processors directly participate in system-wide coherency responses, then cache coherency can be maintained, but communication link speed and bandwidth are insufficient causing delays

Engineering Contradiction:

Improvecache coherencyVSAvoidcommunication link speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

A coherent attached processor proxy (CAPP) is introduced as an intermediary component that participates in system-wide coherency responses on behalf of the attached processor. The CAPP translates system-wide combined responses into internal actions for the attached processor, ensuring compliance with timing requirements of cache coherency protocols while the attached processor communicates through slower or unreliable links.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If attached processors directly access memory blocks, then data synchronization can occur, but bandwidth limitations cause access delays

Engineering Contradiction:

Improvedata synchronizationVSAvoidmemory access speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The CAPP acts as a mediator between the attached processor and the system memory, handling memory access requests and translating system-wide combined responses into internal actions. This intermediary approach ensures data synchronization reliability while overcoming the bandwidth limitations of the attached processor's communication links.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If the system waits for attached processors to respond to coherency requests, then coherency can be maintained, but timing requirements are not met

Engineering Contradiction:

Improvecache coherency protocol complianceVSAvoidcoherency response time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The CAPP is pre-configured to translate system-wide combined responses into internal actions for the attached processor. By preparing the translation mechanism in advance and having the CAPP immediately process responses, the system meets the timing requirements of cache coherency protocols without waiting for the attached processor to directly respond.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The CAPP intermediary processes coherency responses faster than the attached processor could handle them directly, translating system-wide combined responses into internal actions while ensuring protocol compliance. This mediation eliminates timing violations that would occur if the attached processor handled responses directly.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Loss of time

If communication links are improved for attached processors, then coherency response time improves, but system complexity and cost increase

Engineering Contradiction:

Improvecoherency response timeVSAvoidsystem complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

Instead of improving the attached processor's communication links, a CAPP intermediary is introduced that handles the time-critical coherency response translation. This approach achieves fast coherency response times without modifying the attached processor's communication infrastructure, avoiding the complexity and cost of link improvements.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9547597B2Selection of post-request action based on combined response and input from the request source

Publication Date: 2017.01.17 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.