Coherent Block Read Handling for Lower Cache Coherency Latency
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Solution Overview
Problem
Existing multi-node computer systems face high latency in data transfer due to the complexity of cache coherency protocols, particularly in systems utilizing the MOESI protocol, where multiple operations are required to maintain data coherency across different processing nodes.
Innovation Solution
Implementing a coherent memory fabric with early probe caches and probe filters to reduce latency by performing parallel lookups and using a target request globally ordered message (TgtReqGO) to manage data buffer entries efficiently, allowing for faster data retrieval and reduced buffer reservation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherency protocols (MOESI) are implemented to maintain data coherency across processing nodes, then data coherency is maintained, but data transfer latency increases due to multiple operations required
Solution Approach 1:
The patent implements probe filters that pre-process and filter coherency probes before they reach the cache coherence protocol. By performing preliminary filtering of probe requests based on cached information about which caches hold valid data, the system reduces the number of probe operations needed, thereby maintaining data coherency while reducing the time spent on coherency maintenance operations
Solution Approach 2:
The patent introduces probe filters as intermediary components between processing nodes and the cache coherence protocol. These filters act as mediators that intercept, analyze, and filter coherency probes, allowing the system to maintain data coherency through a simplified protocol path that reduces latency compared to the full MOESI protocol operation
2Reliability
If multiple operations are performed to maintain data coherency in MOESI protocol, then data coherency is maintained, but device complexity increases
Solution Approach 1:
The patent segments the cache coherency system into multiple independent components: probe filters, cache memories, and coherence protocol handlers. Each probe filter operates independently on its assigned cache, filtering probes locally before they reach the main coherence protocol. This segmentation reduces the complexity of the overall coherency protocol by distributing the filtering functionality across multiple simple, independent units rather than requiring a single complex protocol mechanism
3Ease of operation
If data is transferred between cache subsystems of different nodes, then data access is enabled, but transfer latency increases
Solution Approach 1:
The patent implements probe filters that perform preliminary analysis of data access requests and pre-filter coherency probes before actual data transfer occurs. By caching information about which caches hold valid data and using this information to filter probes in advance, the system prepares the data access path ahead of time, enabling faster data transfer between cache subsystems when transfers are actually needed
Data Source
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AI summary
A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.