Coherent Cache Fabric Scaling for Active-Core Power Control

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Solution Overview

Problem

The power consumption of processor system integrated circuit packages is a major limiting factor for performance due to heat dissipation challenges in slim form factors, leading to performance bottlenecks as components operate within a limited power budget.

Innovation Solution

Dynamically controlling coherent cache fabric (CCF) utilization by reducing or bypassing it to match active core scenarios, switching between high-performance and low-power modes based on core activity levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the coherent cache fabric is fully operational to maintain high performance, then processing speed is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The coherent cache fabric dynamically adjusts its operational state based on system workload conditions. When few cores are active, the fabric transitions to a reduced power mode with deactivated cache agent instances, minimizing power consumption while maintaining necessary functionality. When more cores become active, the fabric transitions back to full performance mode, ensuring processing speed is maintained when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters of the coherent cache fabric by deactivating specific cache agent instances based on the number of active cores. This parameter change allows the fabric to operate in different states (full performance vs. reduced power) by modifying which components are active, thereby resolving the contradiction between speed and power consumption.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If cache agent instances are deactivated to reduce power consumption, then power usage is improved, but access latency increases

Engineering Contradiction:
Improvepower usageVSAvoidaccess latency
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The coherent cache fabric is segmented into multiple independent cache agent instances, each associated with specific shared cache circuit blocks. This segmentation allows selective deactivation of only those cache agents needed for inactive cores, while keeping cache agents for active cores operational. This resolves the contradiction by minimizing power consumption through selective deactivation while maintaining low latency for active operations.

Inventive Principle:
Principle #1Segmentation

3Use of energy by moving object

If the coherent cache fabric is reduced to lower power consumption, then energy efficiency is improved, but cache capacity decreases

Engineering Contradiction:
Improveenergy efficiencyVSAvoidcache capacity
Core Design Contradiction:
Use of energy by moving objectVSQuantity of substance

Solution Approach 1:

The reduction in cache capacity is localized to only those cache agent instances that are deactivated based on core activity. The cache capacity associated with inactive cores is deactivated, while cache capacity for active cores remains fully available. This local quality approach ensures energy efficiency is improved without unnecessarily reducing the cache capacity needed for active processing operations.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP4625182A1Coherent cache fabric with reduced power mode
Publication Date: 2025.10.01 INTEL CORP
  • EP4625182A1 patent drawingFigure 1
  • EP4625182A1 patent drawingFigure 2A~2B
  • EP4625182A1 patent drawingFigure 3

AI summary

Power may be reduced by dynamically controlling coherent cache fabric (CCF) utilization to efficiently support the number of active cores. In some embodiments, this may be achieved by dynamically reducing or even bypassing the CCF.