Coherent Controller Latency Reduction via CXL Bus Integration
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Solution Overview
Problem
Current storage devices face delays in data transfer due to the need for additional interfaces when accessing coherence buses, which increases latency and reduces input/output operations per second (IOPS) and response time.
Innovation Solution
A storage device with a coherent controller that directly accesses a coherence bus using storage class memory, such as phase change memory or resistive random-access memory, by transferring data to a buffer accessible on the coherence bus, while managing wear leveling and error correction to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If storage devices use additional interfaces to access coherence buses, then data transfer capability is achieved, but latency increases and IOPS decreases
Solution Approach 1:
The patent extracts the storage device's interface from the traditional PCIe/SATA path and directly connects it to the coherence bus (CXL), eliminating intermediate translation layers and reducing latency in data transfer operations
Solution Approach 2:
The patent introduces a coherence buffer as an intermediary structure that sits between the storage device and the coherence bus, enabling efficient data staging and transfer while maintaining coherence protocols, thus resolving the conflict between direct access and protocol compliance
2Productivity
If storage devices use additional interfaces to access coherence buses, then data transfer capability is achieved, but response time increases
Solution Approach 1:
The coherence buffer pre-stages data in advance before it is needed by the processor, allowing data to be ready and waiting in the buffer rather than requiring full data transfer paths to be established at the moment of access, thus improving response time and IOPS
3Loss of time
If storage devices directly access coherence bus, then latency is reduced, but device complexity increases
Solution Approach 1:
The coherence buffer serves multiple functions simultaneously: it acts as a data staging area, a coherence protocol handler, a buffer for wear leveling operations, and a bridge between different memory hierarchies, thus reducing the need for separate dedicated components and managing complexity
Data Source
AI summary
A system includes a bus, at least one processor coupled to the bus, and a storage device coupled to the bus. The storage device includes storage class memory, a buffer; and a controller. The controller is configured to receive an instruction to provide data to the bus. Responsive to receiving the instruction to provide data to the bus, the controller is configured to retrieve data from the storage class memory, update the buffer to represent the data retrieved from the storage class memory, and output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer. The at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.