Coherent Domain Assist Processor for Peripheral I/O Offload
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Solution Overview
Problem
Peripheral I/O devices in traditional computing systems are unable to benefit from the cache-coherent shared-memory multiprocessor paradigm, leading to security and reliability issues due to multiple I/O device drivers and inefficient resource utilization.
Innovation Solution
Implementing a domain assist processor (DAP) and a domain specific accelerator (DSA) in peripheral I/O devices, coupled via a coherent interconnect protocol, allowing them to share the same domain as CPUs and memory in the host computing system, enabling intelligent task offloading and resource management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple I/O device drivers are used to interface with peripheral devices, then device functionality is achieved, but security and reliability issues arise
Solution Approach 1:
The patent introduces a universal processor in the peripheral I/O device that can execute multiple I/O device drivers, allowing a single processor to perform the functions of multiple specialized drivers. This eliminates the need for multiple separate driver implementations while maintaining device functionality, thereby improving security and reliability by reducing the attack surface and integration complexity.
2Ease of operation
If traditional I/O device drivers are used in peripheral devices, then device operation is enabled, but resource utilization efficiency decreases
Solution Approach 1:
The patent segments the functionality of I/O device drivers into separate executable code that can be dynamically loaded and executed on the peripheral device's processor. This allows the host system to offload driver execution to the peripheral device, enabling the host CPU to focus on higher-level tasks while the peripheral processor handles device-specific operations, thereby improving overall resource utilization efficiency.
Solution Approach 2:
The patent introduces a gateway as an intermediary component that facilitates communication between the host system and the peripheral device's processor. The gateway enables the host to execute I/O device drivers on the peripheral device while maintaining system-level access and control, thus improving resource utilization without compromising ease of operation.
3Device complexity
If peripheral I/O devices are excluded from the coherent domain, then hardware complexity is reduced, but resource sharing and efficiency are limited
Solution Approach 1:
The patent merges the peripheral I/O device into the host's coherent domain by extending the coherent interconnect to include the peripheral device's processor and memory. This allows the peripheral device to participate in cache-coherent shared-memory multiprocessor operations, enabling efficient resource sharing and collaboration between host and peripheral processors while maintaining hardware simplicity through unified memory management.
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AI summary
Examples herein describe a peripheral I/O device with a domain assist processor (DAP) and a domain specific accelerator (DSA) that are in the same coherent domain as CPUs and memory in a host computing system. Peripheral I/O devices were previously unable to participate in a cache-coherent shared-memory multiprocessor paradigm with hardware resources in the host computing system. As a result, domain assist processing for lightweight processor functions (e.g., open source functions such as gzip, open source crypto libraries, open source network switches, etc.) either are performed using CPUs resources in the host or by provisioning a special processing system in the peripheral I/O device (e.g., using programmable logic in a FPGA). The embodiments herein use a DAP in the peripheral I/O device to perform the lightweight processor functions that would otherwise be performed by hardware resources in the host or by a special processing system in the peripheral I/O device.