Coherent Fabric Interconnect Supporting Multiple Topologies

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Solution Overview

Problem

The complexity of interconnect architectures in computing systems, particularly in systems-on-a-chip (SoCs), leads to increased costs and design time due to the need for specialized coherent fabrics to support different topologies, which complicates the management of memory coherence and access across multiple devices.

Innovation Solution

A single coherent fabric is designed to support multiple topologies by using mode memory to determine the operating mode and ordering and coherency logic to handle write and read requests, ensuring consistent memory access across CPUs and IPs, thereby eliminating the need for multiple specialized fabrics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If specialized coherent fabrics are used for each topology, then memory coherence and access consistency are ensured, but device complexity and design time increase

Engineering Contradiction:
Improvememory coherenceVSAvoidfabric complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The coherent fabric is designed to support multiple topologies (mesh, ring, hub-and-spoke, dragonfly) through a universal interface and configuration mechanism. The fabric includes mode memory that stores topology identification information and routing logic that can adapt to different topology types, allowing a single fabric structure to perform multiple topology functions rather than requiring separate specialized fabrics for each topology

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple specialized fabrics are supported, then different market segment needs are met, but manufacturing cost and design time increase

Engineering Contradiction:
Improvetopology supportVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The fabric incorporates configurable routing logic and mode memory that enable it to be configured for different topologies based on market segment requirements. This universal design allows the same fabric structure to serve multiple market segments (data center, cloud computing, high-performance computing) without requiring separate specialized fabrics, thereby reducing manufacturing costs while maintaining adaptability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The fabric uses mode memory to store and switch between different topology configuration parameters. By changing the parameters stored in mode memory and adjusting the routing logic configuration, the fabric can adapt to different topology types and market segment requirements without physical reconfiguration or additional hardware, reducing manufacturing complexity and cost

Inventive Principle:
Principle #35Parameter changes

3Reliability

If memory controller is connected directly to coherent fabric, then consistent memory view is achieved, but fabric complexity increases

Engineering Contradiction:
Improvememory consistencyVSAvoidfabric structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces mode memory as an intermediary component between the memory controller and the coherent fabric. The mode memory stores topology identification information and routing parameters that mediate the interaction between the memory controller and different fabric topologies. This intermediary allows the memory controller to maintain consistent memory views across all agents while the fabric structure remains adaptable to different topologies without requiring direct complex connections

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3314445B1Coherent fabric interconnect for use in multiple topologies
Publication Date: 2019.12.25 INTEL IP CORP
  • EP3314445B1 patent drawingFigure 1
  • EP3314445B1 patent drawingFigure 2
  • EP3314445B1 patent drawingFigure 3A

AI summary

An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.