Coherent Interconnect Snoop Unit Ownership Upgrade Processing

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Solution Overview

Problem

Existing systems face unnecessary failures in ownership upgrade requests for cached data, leading to increased transactions due to reliance on contention management circuitry, resulting in false fails and performance inefficiencies.

Innovation Solution

The proposed solution involves using a coherent interconnect with a snoop unit to determine the presence or absence of contention independently of the contention management circuitry, allowing ownership upgrade requests to pass or fail based on whether the data is still held in the processing unit's cache, thereby avoiding false fails and optimizing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the coherent interconnect references the contention management circuitry to process ownership upgrade requests, then contended access can be controlled, but false fails occur and performance decreases due to unnecessary request failures

Engineering Contradiction:
Improveaccuracy of ownership upgrade request processingVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the ownership upgrade request processing into two independent parts: (1) cache state verification performed by the snoop unit to determine if the requesting processor still holds the data in cache, and (2) contention management performed by the contention management circuitry to handle actual contended access. This segmentation allows the snoop unit to provide accurate cache state information independent of contention management, eliminating false fails while maintaining proper contention control.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the coherent interconnect references the snoop unit to determine cache state independently, then false fails are avoided and performance improves, but the complexity of the interconnect increases

Engineering Contradiction:
ImproveperformanceVSAvoidinterconnect complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the snoop unit and contention management circuitry into a single coherent interconnect structure, allowing them to cooperate efficiently. The snoop unit provides cache state verification while the contention management circuitry handles contended access, and both work together within the same interconnect fabric to process ownership upgrade requests without requiring separate independent systems, thus limiting the increase in overall system complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If ownership upgrade requests are processed based on contention management circuitry information, then contended access is controlled, but the number of interconnect transactions increases due to retries

Engineering Contradiction:
Improvecontended access controlVSAvoidnumber of interconnect transactions
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies preliminary action by having the snoop unit verify the cache state of the requesting processor before the ownership upgrade request is fully processed. By checking in advance whether the data is still held in the requester's cache, the system can immediately determine if the request should pass without proceeding through full contention management and potential retry sequences, thus reducing the total number of interconnect transactions while maintaining proper contended access control.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10761987B2Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation
Publication Date: 2020.09.01 ARM LTD
  • US10761987B2 patent drawing
  • US10761987B2 patent drawing
  • US10761987B2 patent drawing

AI summary

An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units. The coherent interconnect may receive, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data. The coherent interconnect is arranged to process the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed. In that event, a pass condition is identified for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.