Coherent Memory Devices With MMU Caches for Lower TLB Misses
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Solution Overview
Problem
Computing systems with large distributed memories face challenges such as long boot times, high translation lookaside buffer (TLB) miss rates, and unreliable, order-non-preserving connections, which hinder performance and reliability.
Innovation Solution
Incorporating features like a memory management unit (MMU) cache, cache coherent protocols, error correction code (ECC), data encryption, and multiple logical device (MLD) support in memory devices to enhance performance, reliability, and order preservation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherent protocols are used in large distributed memory systems, then memory access reliability and order preservation are improved, but boot time increases and TLB miss rates increase
Solution Approach 1:
The memory system is segmented into multiple logical devices (MLD) with independent address spaces and translation lookaside buffers. This segmentation allows different segments to operate independently, reducing the impact of TLB misses in one segment on the overall system performance and boot time
Solution Approach 2:
An MMU cache is introduced as an intermediary component to assist the host TLB. The MMU cache stores recently accessed virtual-to-physical address translations, reducing TLB miss rates and the associated performance penalties without requiring changes to the cache coherent protocol itself
2Reliability
If MMU cache is added to assist TLB performance, then TLB miss rate decreases, but device complexity increases
Solution Approach 1:
The MMU cache is designed to serve multiple functions: it acts as a TLB assistant for address translation, supports quality of service requirements through configurable policies, and provides a unified interface for handling virtual-to-physical address mappings across multiple logical devices. This multi-functionality justifies the added complexity by delivering diverse benefits from a single component
3Adaptability or versatility
If multiple logical device support is implemented, then address space management flexibility improves, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple logical devices, each with its own address space and translation lookaside buffer. This segmentation provides flexible address space management for different applications or workloads while isolating their operations, preventing complexity from propagating across the entire system
Solution Approach 2:
Each logical device maintains its own translation lookaside buffer and can independently manage its address translations. This self-service approach reduces the burden on the host system and allows parallel processing of address translations across multiple logical devices, offsetting the complexity through distributed management
Data Source
AI summary
A coherent memory system. In some embodiments, the coherent memory system includes a first memory device. The first memory device may include a cache coherent controller; a volatile memory controller; a volatile memory; a nonvolatile memory controller; and a nonvolatile memory. The first memory device may be configured to receive a quality of service requirement and to selectively enable a first feature in response to the quality of service requirement.