Coherent Memory Low Power State Stall Avoidance
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Solution Overview
Problem
Coherent memory devices entering low power states can cause host processor stalls, leading to performance degradation and increased energy consumption, which may not comply with energy regulations.
Innovation Solution
A memory subsystem manages page table entries to allow coherent memory to enter low power states without stalling the host processor by invalidating page table entries, triggering page faults, and using fault routines to handle memory access asynchronously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If coherent memory enters low power states, then energy consumption is reduced, but host processor stalls occur causing performance degradation
Solution Approach 1:
The system performs preliminary actions by invalidating page table entries before the coherent memory device enters low power state. This preparation ensures that when the device wakes up, the host processor can immediately resume operation without stalling, thus enabling energy savings while maintaining performance.
Solution Approach 2:
The page table entry acts as an intermediary mechanism between the coherent memory device and the host processor. By manipulating this intermediary structure, the system decouples the power state changes of the memory device from the continuous operation requirements of the processor, allowing both to function independently without causing stalls.
2Productivity
If coherent memory is prevented from entering low power states, then host processor performance is maintained, but energy consumption increases
Solution Approach 1:
The system performs preliminary actions by invalidating page table entries before the coherent memory device enters low power state. This preparation ensures that when the device wakes up, the host processor can immediately resume operation without stalling, thus enabling energy savings while maintaining performance.
Solution Approach 2:
The page table entry acts as an intermediary mechanism between the coherent memory device and the host processor. By manipulating this intermediary structure, the system decouples the power state changes of the memory device from the continuous operation requirements of the processor, allowing both to function independently without causing stalls.
3Productivity
If page table entries are invalidated before low power state, then processor stalls are avoided, but additional memory management complexity is introduced
Solution Approach 1:
The page table entry invalidation mechanism serves multiple functions: it enables low power state entry, prevents processor stalls, and provides a foundation for asynchronous fault handling. By making this single mechanism multi-functional, the system avoids adding separate complex subsystems while achieving multiple objectives simultaneously.
Solution Approach 2:
The memory management system leverages existing page table infrastructure to achieve low power state management. Instead of adding a completely new mechanism, the system reuses and extends the page table functionality, allowing the existing structure to serve dual purposes and reducing overall system complexity.
Data Source
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AI summary
A memory subsystem with memory managed with coherent access can manage page table entries to enable putting the memory in a low power state. The memory control can change a page table entry for the memory prior to triggering the memory to enter the low power state. The change to the page table entry will cause a page fault for a subsequent access to the memory. The page fault will trigger handling the access to the memory with a fault routine, avoiding synchronous delay to the memory that would occur with normal access.