Coherent Write Circuit Flow for Lower CXL Host Latency
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Solution Overview
Problem
Configurable logic integrated circuits, such as FPGAs, experience high latency and performance bottlenecks in CXL coherent write requests due to inherent latency in CXL-based coherent interfaces and round-trip handshakes, especially when slower logic circuitry interacts with faster host systems.
Innovation Solution
Implementing a push-write flow where slower logic circuitry issues a write command and data to faster logic circuitry, which then transmits the command to the host system, storing data until a write pull response is received, and subsequently sends data back to the host, using unique identifiers to manage and synchronize requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional write-pull flow is used in CXL coherent interfaces, then protocol compliance is maintained, but write request latency increases significantly
Solution Approach 1:
The patent applies preliminary action by having the device send the write data to the host system in advance, before receiving the write response. The host system stores the write data in a buffer upon receiving the write command, and the device can subsequently send additional write data or receive write responses without waiting for acknowledgments, thereby reducing latency while maintaining protocol compliance.
Solution Approach 2:
The patent introduces a buffer as an intermediary component in the host system that temporarily stores write data. This buffer acts as a mediator between the device and the host system's memory, allowing the device to operate independently without being blocked by the slower response times of the host system, thus reducing overall write request latency.
2Productivity
If multiple write requests are processed simultaneously in slower logic circuitry, then productivity increases, but head-of-line blocking occurs
Solution Approach 1:
The patent applies segmentation by dividing the write request processing into independent units that can be tracked individually using unique identifiers. Each write request is assigned a unique identifier that allows the host system to manage and track multiple concurrent requests without head-of-line blocking, enabling parallel processing while maintaining request integrity.
Solution Approach 2:
The patent implements feedback mechanisms where the host system sends write responses back to the device with corresponding unique identifiers. This feedback loop allows the device to track the status of multiple write requests and manage them efficiently, increasing productivity while avoiding the complexity of content addressable memory structures.
Data Source
AI summary
A circuit system includes slow running logic circuitry that generates write data and a write command for a write request. The circuit system also includes fast running logic circuitry that receives the write data and the write command from the slow running logic circuitry. The fast running logic circuitry stores the write data and the write command. A host system generates a write response in response to receiving the write command from the fast running logic circuitry. The host system sends the write response to the fast running logic circuitry. The fast running logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the slow running logic circuitry.