Coil Component Manufacturing via Direct Patterning
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Solution Overview
Problem
Existing coil components face challenges in miniaturization and cost-effectiveness due to high manufacturing costs and low productivity, along with high coil loss rates and reduced line margin in forming thin film type coil components using semi-additive processes, which are exacerbated by flash etching issues.
Innovation Solution
A coil component design featuring a first coil layer with a conductive layer formed without a seed layer and a second coil layer with a seed layer covering inner surfaces, improving manufacturing efficiency and reducing coil loss rates by eliminating the need for separate photosensitive materials and enhancing fine line resolution through direct patterning of insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If semi-additive process with flash etching is used to form coil patterns, then coil patterns can be formed on board, but manufacturing costs increase and productivity decreases
Solution Approach 1:
The patent extracts and removes the photosensitive material for insulation from the manufacturing process. Instead of using photosensitive materials to define coil patterns and then removing them via flash etching, the invention directly forms conductive layers on the board in predetermined coil patterns without requiring photosensitive materials or flash etching steps, thereby eliminating these problematic processes entirely
Solution Approach 2:
The patent performs preliminary actions by directly forming conductive layers in the desired coil patterns on the board without needing to first create photosensitive patterns. The conductive layers are deposited directly where needed, eliminating the need for subsequent removal processes and improving manufacturing efficiency
2Ease of manufacture
If flash etching is used to remove photosensitive materials, then insulation and seed layer removal is achieved, but lower layer flatness is compromised reducing line margin
Solution Approach 1:
The patent extracts and removes the flash etching process entirely from the manufacturing sequence. By directly depositing conductive layers in the desired patterns without using photosensitive materials that require flash etching for removal, the invention eliminates the damage to lower layer flatness and preserves line margins
Solution Approach 2:
The patent uses the board's existing surface features (such as pad holes and via holes) as templates or copies to guide the direct formation of conductive layers. This approach allows precise pattern formation without requiring photosensitive materials and flash etching, thereby maintaining lower layer flatness and adequate line margins
3Ease of manufacture
If semi-additive process is used to form coil patterns, then coil patterns can be formed, but coil loss rate increases
Solution Approach 1:
The patent extracts and eliminates the flash etching step from the manufacturing process. By directly forming conductive layers in predetermined coil patterns without flash etching, the invention prevents the damage and irregularities that would otherwise increase coil resistance and energy loss
Solution Approach 2:
The patent performs preliminary direct deposition of conductive materials in the exact final pattern configuration. This eliminates the need for flash etching that causes damage to the conductive paths, thereby reducing coil loss rate by maintaining continuous, intact conductive layers with minimal resistance
Data Source
AI summary
A coil component includes: a coil part including a first coil layer and a second coil layer disposed above the first coil layer, wherein the first coil layer includes a first insulating layer having a first opening pattern and a first conductive layer disposed in the first opening pattern, and the second coil layer includes a second insulating layer having a second opening pattern, a seed layer covering inner side surfaces and a lower surface of the second opening pattern, and a second conductive layer disposed in the second opening pattern.


