Miniaturized Coil Component Layout With Thin Seed Layer Plating
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Solution Overview
Problem
The challenge is to maintain the performance and reliability of coil electronic components as they are miniaturized, particularly in reducing the size while ensuring the magnetic and electrical properties are not compromised, and to minimize the impact on the support substrate and other components during processing.
Innovation Solution
A coil electronic component design featuring a support substrate with a thin seed layer and multiple plating layers, where the seed layer has a thickness of 1.5 μm or less, and the plating layers are configured to reduce the gap between coil patterns, with an encapsulant covering the substrate and coil pattern, and external electrodes connected to the coil pattern, allowing for a reduced size without sacrificing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of the coil electronic component is reduced, then the component size decreases, but the performance and reliability deteriorate
Solution Approach 1:
The patent applies parameter changes by precisely controlling the thickness of the seed layer (1.5 μm or less) and the coil pitch distance (35 μm or less between adjacent turns). These parameter optimizations enable reduced component size while maintaining sufficient magnetic properties and electrical performance, resolving the contradiction between miniaturization and reliability
Solution Approach 2:
The patent utilizes the thickness dimension by forming a multi-layer structure with seed layer and plating layer, where the coil pattern is disposed on the support substrate with controlled vertical stacking. This dimensional approach allows compact design while preserving functional performance
2Volume of moving object
If the gap between coil patterns is reduced, then the component size decreases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent sets the coil pitch distance parameter to 35 μm or less between outer side surfaces of adjacent turns, and controls the seed layer thickness to 1.5 μm or less. These optimized parameters enable tight spacing while maintaining manufacturability through standard plating processes
Solution Approach 2:
The patent forms a seed layer before the plating layer to prepare the substrate for subsequent plating processes. This preliminary action ensures uniform plating deposition even at reduced pitch distances, facilitating precise coil pattern formation with tight spacing
3Volume of moving object
If the seed layer thickness is reduced, then the gap between coil patterns decreases, but the plating quality may deteriorate
Solution Approach 1:
The patent optimizes the seed layer thickness to 1.5 μm or less while maintaining adequate plating quality. This parameter optimization balances the need for reduced gap between coil patterns with the requirement for sufficient nucleation surface area to support uniform plating layer formation
Solution Approach 2:
The patent uses a composite structure consisting of a seed layer and a plating layer. The seed layer serves as a foundation that promotes uniform plating deposition, while the plating layer provides the final functional coating. This composite approach maintains plating quality even with reduced seed layer thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the securement of sufficient performance and reliability even at reduced sizes by optimizing the thickness of the seed layer, plating layers, and encapsulant, improving inductance and direct current resistance properties while reducing process impacts on the support substrate.
Implementation Method 1
the coil pattern includes a seed layer having a thickness of 1.5 μm or less and a plating layer disposed on the seed layer
Data Source
AI summary
A coil electronic component includes a support substrate, a coil pattern disposed on the support substrate, an encapsulant encapsulating at least portions of the support substrate and the coil pattern, and external electrodes disposed externally on the encapsulant and connected to the coil pattern. The coil pattern includes a seed layer having a thickness of 1.5 μm or less and a plating layer disposed on the seed layer.