Cold Data Transfer via Dedicated Fuse Bus in Memory Devices
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Solution Overview
Problem
High-speed memory devices like DRAM face challenges in managing memory space efficiently, leading to performance degradation due to full capacity issues when multiple applications are open simultaneously, as users must manually stop unused applications to free up memory.
Innovation Solution
A memory system that includes a controller, DRAM, and non-volatile storage (NVS) where cold data is transferred from DRAM to NVS using a dedicated cold data transfer control bus, allowing concurrent data transfer without interfering with normal memory access, using a separate data bus like the fuse bus to manage memory full alerts and optimize memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cold data transfer is performed using the existing data bus, then memory space is freed up, but normal memory access operations are interfered with and system performance degrades
Solution Approach 1:
The patent divides the data transfer function into two separate channels: a first data bus for normal memory access operations and a second data bus for cold data transfer. This segmentation allows both functions to operate simultaneously without interfering with each other, resolving the contradiction between freeing memory space and maintaining reliable memory access.
Solution Approach 2:
The patent introduces a second data bus as an intermediary channel specifically for cold data transfer. This intermediary structure enables the system to transfer cold data to non-volatile storage without impacting the primary data bus that handles normal memory access operations, thus maintaining system reliability while freeing up memory space.
2Quantity of substance
If manual intervention is required to stop unused applications, then memory space is freed up, but user convenience and system automation are reduced
Solution Approach 1:
The patent implements automatic cold data transfer functionality that operates without user intervention. The system autonomously identifies cold data, determines when memory space is needed, and transfers appropriate data to non-volatile storage, enabling the memory management system to serve itself and eliminating the need for manual application management by users.
Solution Approach 2:
The patent employs a feedback mechanism where the system continuously monitors memory usage and application activity patterns. Based on this feedback, the system automatically determines when and what cold data to transfer, creating a closed-loop control system that dynamically manages memory space without requiring user input or manual intervention.
3Reliability
If a separate cold data transfer bus is implemented, then memory access operations are not interfered with, but device complexity increases
Solution Approach 1:
The patent designs the second data bus to serve multiple functions: it handles cold data transfer to non-volatile storage and can potentially serve other specialized data transfer needs. This multi-functionality justifies the added complexity by providing a dedicated channel that improves reliability without requiring entirely separate infrastructure for each function.
Data Source
AI summary
In some examples, a system may include a plurality of memory blocks, a first data bus coupled to the plurality of memory blocks in a memory device, a second data bus coupled to the plurality of memory blocks, a controller configured to perform memory read and write operations on the plurality of memory blocks via the first data bus, and a non-volatile storage (NVS) data transfer circuit configured to transfer data in a first memory block of the plurality of memory blocks to a NVS device via the second data bus. The first memory block may be a cold data block least accessed among the plurality of memory blocks. The cold data transfer may be performed via the second data bus when a different memory block is being accessed via the first data bus concurrently. The second data bus may be a fuse bus in the memory device.