Cold Memory Dependency Identification for Out-of-Order Processors
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Solution Overview
Problem
Conventional processor devices face limitations in out-of-order execution due to memory dependencies between instructions, particularly read-after-write hazards, which can lead to inefficient performance and pipeline recovery, and existing dependency predictor circuits provide limited coverage and require training on previous hazards.
Innovation Solution
Implement a dependency identifier circuit with a store instruction queue to identify memory dependencies between store and load instructions without prior hazards, using a store instruction queue to store physical register numbers, immediate values, and age indicators, and establish dependencies using conventional mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If out-of-order execution is implemented to improve processor efficiency, then productivity increases, but read-after-write hazards occur causing pipeline recovery and performance degradation
Solution Approach 1:
The patent applies preliminary action by proactively identifying memory dependencies between store and load instructions before executing the load instruction. The dependency identifier circuit checks for potential read-after-write hazards in advance by comparing the load instruction's target address against recently executed store instructions, and if a dependency is detected, the load instruction is held in the instruction queue until the store instruction completes, thereby preventing pipeline recovery operations
2Reliability
If a dependency predictor circuit is used to avoid RAW hazards, then reliability improves, but the circuit requires training on previous hazards and provides limited coverage
Solution Approach 1:
The patent replaces the reactive dependency predictor circuit with a proactive dependency identification approach. Instead of waiting for RAW hazards to occur and then training the predictor, the new circuit continuously monitors and identifies potential memory dependencies before they manifest as hazards. This is achieved by maintaining a queue of recent store instructions with their target addresses and comparing each load instruction's target address against this queue, thereby providing comprehensive coverage without requiring training on previous hazards
3Reliability
If warm memory dependency prediction is implemented, then some hazards are avoided, but the predictor must first detect RAW hazards before establishing dependencies limiting its effectiveness
Solution Approach 1:
The patent eliminates the training time requirement by implementing cold dependency identification that proactively detects memory dependencies before any RAW hazard occurs. The circuit maintains a store instruction queue containing target addresses of recently executed store instructions and performs address comparison with incoming load instructions to identify dependencies in advance, allowing immediate enforcement of in-order execution without needing to first observe and learn from actual hazard occurrences
Data Source
AI summary
Performing “cold” memory dependency identification in processor devices is disclosed herein. In some aspects, a processor device includes a dependency identifier circuit comprising a store instruction queue. The dependency identifier circuit detects a store instruction comprising a single store address register number and a store immediate value in an instruction processing circuit front end. The dependency identifier circuit writes a store physical register number, the store immediate value, and an age indicator in an entry of the store instruction queue. The dependency identifier circuit detects a load instruction comprising a single load address register number and a load immediate value in the instruction processing circuit front end. The dependency identifier circuit determines whether an entry of the store instruction queue stores a corresponding load physical register number and the load immediate value, and, if so, establishes a dependency between the load instruction and a store instruction corresponding to the entry.