Integrated Cold Plate With Backside Signal Redistribution
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Solution Overview
Problem
Current integrated cooling systems for microelectronic devices face challenges in thermal dissipation and signal routing due to increased power density and compact chip layouts, where backside wiring can interfere with thermal dissipative systems and occupy valuable space, limiting their ability to meet thermal budgets in large-scale computing systems.
Innovation Solution
The implementation of integrated cooling assemblies with a signal redistribution network on the backside of the device, which includes a cold plate with stacked and bonded layers forming a coolant channel and a signal redistribution network that communicatively couples devices without interfering with the thermal pathway, allowing for efficient power and ground delivery and signal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If backside wiring is implemented for signal routing, then signal distribution capability is improved, but thermal dissipation performance deteriorates due to interference with the thermal dissipative system
Solution Approach 1:
The patent implements signal routing through the thickness dimension of the substrate rather than laterally on the backside surface. Through-substrate vias penetrate the substrate vertically to establish electrical connections, transforming a 2D backside routing problem into a 3D solution that utilizes the substrate's thickness dimension. This eliminates interference with thermal dissipative systems while maintaining signal distribution capability.
2Adaptability or versatility
If redistribution layer is added on the frontside of the chip, then signal routing flexibility is improved, but valuable active area is occupied and form factor increases
Solution Approach 1:
The patent extracts the signal routing function from the frontside active area and relocates it to the backside of the chip. By implementing through-substrate vias and backside signal pads, the redistribution functionality is separated from the active circuit area, allowing the frontside to be fully utilized for active components while signal routing is handled on the backside.
3Productivity
If compact chip layout is implemented to meet computing demands, then processing density is improved, but power density increases and thermal dissipation becomes more difficult
Solution Approach 1:
The patent segments the chip structure into distinct functional zones: active circuitry on the frontside and signal routing/thermal management infrastructure on the backside. Through-substrate vias are strategically segmented and distributed to create efficient thermal pathways that connect hot spots on the frontside to heat sinks on the backside, enabling independent optimization of both processing density and thermal dissipation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces thermal resistance and enables effective signal distribution between devices while maintaining thermal efficiency, enhancing the cooling performance and reducing the form factor of microelectronic devices.
Implementation Method 1
integrated cooling assemblies providing signal redistribution and fluid cooling
Implementation Method 2
the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the first side of the plurality of stacked and bonded layers and the semiconductor device
Implementation Method 3
the integrated device cooling assemblies reduce resistance in the thermal path
Data Source
AI summary
The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.