Backside Cold Plate Interconnects for Chip Cooling and Signal Routing
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Solution Overview
Problem
Current integrated cooling systems for microelectronic devices face challenges in thermal dissipation due to increased power density and compact chip layouts, where backside wiring interferes with thermal dissipative systems, and existing redistribution layers lack flexibility to couple active circuitries at different pitches, leading to inadequate thermal budgets in large-scale computing systems.
Innovation Solution
The implementation of integrated cooling assemblies with a signal redistribution network on the backside of the device, comprising stacked and bonded layers that form a cold plate with a coolant channel, allowing for direct hybrid bonding and thru-interconnects to reduce thermal resistance and distribute signals without interfering with the thermal pathway, while providing power and ground delivery networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If backside wiring is implemented for signal redistribution, then signal routing flexibility is improved, but thermal dissipation performance deteriorates due to interference with the thermal dissipative system
Solution Approach 1:
The patent implements signal redistribution by routing signals through the thickness dimension of the substrate rather than laterally on the backside surface. Through-substrate vias conduct signals from frontside pads through the substrate thickness to backside contact regions, eliminating interference with thermal dissipative systems while maintaining signal routing flexibility.
2Adaptability or versatility
If redistribution layer is added on the frontside to support data traffic demand, then signal routing capability is improved, but valuable active side area is occupied and form factor increases
Solution Approach 1:
The patent inverts the conventional approach by moving signal redistribution functionality from the frontside to the backside of the substrate. Backside contact regions and through-substrate via structures provide signal routing capabilities on the backside, freeing up valuable frontside active area while maintaining the required signal routing capability for data traffic demand.
3Area of stationary object
If compact chip layout is implemented to meet computing demands, then area efficiency is improved, but power density increases and thermal flux increases leading to elevated chip temperatures
Solution Approach 1:
The patent extracts signal routing functions from the frontside active area and relocates them to the backside through through-substrate vias and backside contact regions. This extraction allows compact chip layout for improved area efficiency while the separated backside signaling path does not interfere with thermal dissipative systems, enabling effective thermal management despite high power density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces thermal resistance and enables efficient signal distribution between devices, enhancing thermal management and communication without compromising thermal performance, thus addressing the thermal budget challenges in high-power density microelectronic systems.
Implementation Method 1
The plurality of stacked and bonded layers may comprise a first interconnect vertically disposed through the support feature, wherein the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the first side of the plurality of stacked and bonded layers and the semiconductor device
Implementation Method 2
The first side of the plurality of stacked and bonded layers and the backside of the device define a coolant channel therebetween
Data Source
AI summary
The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.