Cold-Sparing CMOS Circuits for Leakage Isolation and Redundancy
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Solution Overview
Problem
Electronic systems operating in harsh environments face failures due to extreme temperatures and radiation, leading to inefficiencies in power consumption in backup units, particularly in cold-sparing configurations where leakage currents result in wasted power and reduced performance.
Innovation Solution
The implementation of low-leakage output stages and input latch circuits using back-to-back PMOS transistors to block leakage currents, along with low power dissipation ESD protection circuits and majority voting output circuits, ensures minimal power consumption and fault tolerance in cold-sparing configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cold-sparing configuration is employed with multiple functional units connected in parallel, then system reliability is improved through redundancy, but power consumption increases due to leakage currents in backup units
Solution Approach 1:
The patent extracts and removes the harmful leakage current paths from the cold-spared backup units by implementing isolation circuits that disconnect the backup units' output stages from the common output bus when they are not actively driving. This extraction of the harmful element (leakage current) allows the backup units to remain powered for immediate failover while consuming minimal power.
Solution Approach 2:
The patent introduces intermediary isolation circuits including transmission gates and tri-state buffers that act as mediators between the cold-spared units and the common output bus. These intermediaries block leakage currents while allowing signal transmission when needed, thus resolving the contradiction between maintaining backup readiness and minimizing power consumption.
2Loss of time
If cold-spared backup units are kept powered for immediate failover, then switching time is reduced, but leakage currents create loading effects on the active unit's output
Solution Approach 1:
The patent extracts the harmful loading effect by removing the leakage current paths from the cold-spared units through isolation circuits. By disconnecting the backup units' output stages from the common output bus when they are not actively driving, the harmful loading effect is eliminated while the units remain powered for immediate failover.
Solution Approach 2:
The patent introduces intermediary isolation circuits including transmission gates and tri-state buffers that act as mediators between the cold-spared units and the common output bus. These intermediaries block leakage currents and prevent loading effects while allowing rapid signal transmission when failover is required.
3Use of energy by moving object
If isolation circuits are added to block leakage currents, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent implements multi-functional isolation circuits that serve multiple purposes: blocking leakage currents, preventing loading effects, and enabling rapid failover. The transmission gates and tri-state buffers perform both isolation and signal transmission functions, reducing the need for additional dedicated components and thereby limiting the increase in circuit complexity.
Solution Approach 2:
The patent merges the isolation function with the existing output stage circuitry by integrating transmission gates and tri-state buffers into the backup units' output paths. This combining of functions reduces the overall circuit complexity compared to adding separate isolation circuits for each backup unit.
Data Source
AI summary
CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.