Cold-Sprayed Aluminum Capacitors for 3D Power Package Integration
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Solution Overview
Problem
Current power module technologies face limitations in achieving high power densities and efficiencies due to the use of low-volumetric-capacitance-density capacitors, leading to large electrical and thermal impedances, and reliability concerns in high electric field, high-temperature environments, which restrict the performance of computing, IoT, and communication systems.
Innovation Solution
The development of high-capacitance-density capacitors using additive manufacturing and packaging processes, specifically patterning valve metals like tantalum and aluminum on copper foils, with 3D integration and anodization techniques, to create porous electrodes with high surface areas, reducing the need for post-patterning and sintering, and enabling direct integration into packaging substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional low-volumetric-capacitance-density capacitors are used in power modules, then manufacturing and assembly are straightforward, but power density and efficiency are limited due to large electrical and thermal impedances
Solution Approach 1:
The patent transitions from planar capacitor designs to three-dimensional vertical capacitor structures. By stacking multiple capacitor layers vertically and utilizing vertical interconnects, the invention achieves higher capacitance density within the same footprint, reducing the number of discrete components needed and lowering overall electrical and thermal impedance in the power module
Solution Approach 2:
The invention integrates passive capacitor structures directly into the power module substrate, merging previously separate discrete capacitor components with the active device mounting substrate. This consolidation reduces the number of interconnects and assembly steps, thereby lowering electrical and thermal impedance while improving power density
2Productivity
If pre-packaged devices and low-volumetric capacitance-density capacitors are assembled, then integration is simple, but system integration limitations prevent reaching high power densities and efficiencies
Solution Approach 1:
The patent segments the power module into functional zones with capacitors strategically positioned near their respective load points. By dividing the capacitor array into multiple smaller units distributed across the substrate, the invention reduces current path lengths and electrical impedance while maintaining manufacturability through standardized segmentation patterns
Solution Approach 2:
The invention utilizes vertical stacking of capacitor layers to achieve higher capacitance density without increasing footprint area. This three-dimensional integration approach overcomes the limitations of planar assembly while maintaining compatibility with standard packaging processes
3Ease of manufacture
If discrete capacitors are used, then assembly is straightforward, but large electrical impedances exist between loads, switches and drivers
Solution Approach 1:
The patent merges the capacitor structures with the power module substrate by forming capacitors directly on the substrate using the same semiconductor fabrication processes. This integration eliminates discrete component mounting and reduces the number of interconnects, thereby lowering electrical impedance while maintaining assembly simplicity
Solution Approach 2:
The capacitor structures are formed during the substrate fabrication process itself, before final module assembly. By preliminarily creating the capacitor structures as part of the substrate, the invention reduces subsequent assembly steps and minimizes the introduction of additional electrical impedance interfaces
4Quantity of substance
If traditional capacitor designs are used, then manufacturing is conventional, but capacitance density is insufficient for next-generation power deliver networks
Solution Approach 1:
The patent employs porous dielectric materials in the capacitor structures to achieve higher capacitance density. The porous structure provides increased surface area for charge storage within the same volume, significantly boosting capacitance density while using standard dielectric deposition processes
Solution Approach 2:
The invention uses composite structures combining different dielectric materials with complementary properties. By stacking layers of high-k dielectrics and porous materials, the patent achieves high capacitance density while maintaining compatibility with conventional semiconductor fabrication processes
5Volume of moving object
If high-capacitance-density capacitors are integrated, then miniaturization is enabled, but fabrication precision requirements increase
Solution Approach 1:
The patent segments the high-precision patterning into multiple lithography steps with standard resolution. By using sequential patterning steps rather than requiring a single high-resolution step, the invention achieves fine feature sizes with conventional lithography tools, reducing manufacturing precision requirements while enabling miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in capacitors with enhanced capacitance density, reduced thickness, lower fabrication costs, and improved reliability, enabling miniaturization and efficient thermal management, potentially achieving 10× higher capacitance-density than existing high-voltage capacitors with high-temperature stability and ripple current handling.
Implementation Method 1
They have a common characteristic of forming a natural and native oxide that is highly insulating in nature
Implementation Method 2
Additively-deposited tantalum and aluminum nanoparticles on copper foils for 3D integration of high-surface-area electrodes
Implementation Method 3
Anodization and conducting polymer cathodes providing reduced cost
Data Source
AI summary
Cold-sprayed aluminum capacitors on lead frame metal foils are provided for applications in 3D power package integration. This additive manufacturing process allows pre-patterned low-temperature processing of aluminum electrodes on metal lead frames, insulated metal substrates or even heat-spreaders and cold-plates. Cold-sprayed capacitors can eliminate several process integration and reliability issues that are associated with traditional discrete surface-assembled capacitors.