Collaborative Clock Recovery for Multi-Channel Jitter Tracking

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Solution Overview

Problem

Current clock and data recovery systems face challenges in accurately synchronizing multiple high-speed serial data streams without accompanying clock signals, particularly in tracking high-frequency jitter and aligning local clocks to specific data streams.

Innovation Solution

A communication system with integrated circuit devices employs collaborative clock and data recovery methods, where multiple receivers share phase-error signals to make common phase adjustments to a frequency reference clock, and local adjustments are made to track specific jitter, using data samplers and clock recovery circuits to synchronize data streams.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple receivers independently perform clock and data recovery on multiple high-speed serial data streams, then each receiver can synchronize its local clock to its specific data stream, but the system cannot effectively track high-frequency jitter common across multiple channels

Engineering Contradiction:
Improvejitter tracking accuracyVSAvoidcommon phase adjustment capability
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent combines phase-error signals from multiple independent clock and data recovery circuits into a single common phase adjustment signal. This merging allows the system to track high-frequency jitter that appears across multiple channels by aggregating phase error information, while each receiver maintains its own local adjustments for channel-specific variations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the clock and data recovery function into two parts: a common phase adjustment applied to all receivers based on combined phase-error signals, and local phase adjustments specific to each receiver. This segmentation enables differentiated handling of common-mode jitter versus channel-specific timing variations.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If a single reference clock is used for multiple data streams, then clock distribution is simplified, but the system cannot align local clocks to specific data streams with different timing characteristics

Engineering Contradiction:
Improveclock distribution complexityVSAvoidper-channel clock alignment
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent makes the clock distribution system dynamic by allowing the reference clock to be phase-adjusted based on feedback from multiple receivers. The system adapts the common phase adjustment in real-time to match the timing characteristics of specific data streams, enabling flexible alignment without requiring multiple fixed reference clocks.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback loops where each receiver monitors its phase error and contributes to adjusting the common reference clock. This feedback mechanism allows the system to automatically align the reference clock to the timing characteristics of active data streams while maintaining simplified clock distribution architecture.

Inventive Principle:
Principle #23Feedback

3Reliability

If phase-error signals from multiple receivers are combined for common phase adjustment, then high-frequency jitter tracking improves, but the processing complexity and signal integration requirements increase

Engineering Contradiction:
Improvejitter tracking reliabilityVSAvoidphase error signal processing
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent creates a universal common phase adjustment circuit that processes phase-error signals from multiple receivers and applies a single adjusted clock signal to all channels. This multi-functional circuit handles both common-mode jitter correction and maintains compatibility with existing per-receiver timing requirements, reducing overall system complexity despite the added coordination.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10348480B2Collaborative clock and data recovery
Publication Date: 2019.07.09 RAMBUS INC
  • US10348480B2 patent drawing
  • US10348480B2 patent drawing
  • US10348480B2 patent drawing

AI summary

A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.