Collapsed Parse Tree for HDL Simulation Memory Reduction
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Solution Overview
Problem
The increasing complexity and size of high-level circuit designs in hardware descriptive languages (HDLs) lead to significant memory requirements during the elaboration process for synthesis or simulation, which is inefficient and resource-intensive.
Innovation Solution
A process is implemented where multiple instances of a module in a circuit design are represented by a single representative parse node in the parse tree, with instance-specific data structures and memory allocation, reducing the need for extensive memory usage by collapsing the parse tree and using reference pointers to instance-specific data structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional elaboration processes are used for HDL designs, then complete functional simulation can be achieved, but memory requirements increase significantly
Solution Approach 1:
The parse tree is segmented into representative nodes that group multiple identical module instances together. Instead of creating separate parse tree entries for each instance, the patent segments them into unified representative nodes with instance-specific data structures, reducing memory consumption while preserving functional simulation accuracy.
Solution Approach 2:
Representative parse nodes serve multiple functions: they represent entire groups of identical module instances, store shared module information, and maintain references to instance-specific data structures. This multi-functionality eliminates redundant storage and reduces overall memory requirements during elaboration.
2Ease of operation
If multiple instances of modules are represented individually in the parse tree, then detailed instance tracking is enabled, but memory consumption increases
Solution Approach 1:
Instance tracking is segmented between representative nodes (for shared module information) and instance-specific data structures (for individual instance details). This segmentation maintains complete instance tracking capability while avoiding redundant storage of identical module information across multiple instances.
Solution Approach 2:
Instance-specific data structures act as intermediaries between representative parse nodes and individual module instances. These intermediary structures enable detailed instance tracking and connectivity information storage without requiring separate full parse tree entries for each instance, thus reducing overall memory consumption.
3Loss of information
If full parse trees are created for each module instance, then complete connectivity information is stored, but elaboration memory requirements become prohibitive
Solution Approach 1:
Connectivity information is extracted from the representative parse nodes and stored in separate instance-specific data structures. This extraction removes redundant connectivity information from multiple identical instances while preserving complete connectivity data in the instance-specific structures, reducing elaboration memory requirements.
Solution Approach 2:
Instead of creating full parse tree copies for each instance, the patent creates lightweight instance-specific data structures that contain only the necessary instance-specific connectivity information. These copied structures reference the shared representative node, maintaining information completeness while dramatically reducing memory usage.
Data Source
AI summary
During the elaboration and synthesis of a circuit design, a parse tree generally must be fully expanded to access memory resources and data of individual module instances in order to perform optimizations that will result in better runtime performance of generated simulation code. The present invention reduces memory requirements in generating simulation or emulation executable code by implementing a collapsed parse tree, where multiple instances of a module in a HDL design are represented by a single representative node in the parse tree.