Collapsible Gate for Graphene and CNT Transistors
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Solution Overview
Problem
The challenge in fabricating field effect transistors with graphene and carbon nanotubes lies in depositing a thin, pinhole-free gate dielectric layer, as existing materials and techniques either result in overly thick films or damage the channel material, reducing charge mobility and device performance.
Innovation Solution
A disposable material layer is used, which is less inert than graphene or carbon nanotubes, allowing for the deposition of a contiguous dielectric layer and gate conductor stack, shielding the channel material during processing and enabling selective etching to form a free-standing gate structure that contacts the channel surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sufficient amount of dielectric material is deposited to coat the surface contiguously, then a continuous film is formed, but the gate dielectric film becomes overly thick
Solution Approach 1:
The gate dielectric structure is segmented into two parts: a thin first gate dielectric layer deposited directly on the carbon nanotube, and a second gate dielectric layer deposited on top. This segmentation allows the first layer to provide intimate contact with the channel for good electrostatics, while the second layer provides additional dielectric thickness without compromising the thin interface layer.
Solution Approach 2:
The solution moves from attempting to form a single thin layer to forming multiple layers in the vertical dimension. By stacking dielectric layers, the patent achieves both thinness at the critical interface and sufficient total thickness, resolving the contradiction through dimensional arrangement.
2Ease of manufacture
If the surface of graphene or CNT is functionalized to make it more chemically active, then dielectric deposition effectiveness is enhanced, but the quality of channel material is reduced
Solution Approach 1:
The patent applies preliminary surface treatment to the substrate (insulator layer) rather than to the carbon nanotube channel itself. By functionalizing the substrate surface with oxygen plasma or chemical treatment, the patent creates nucleation sites for dielectric deposition without exposing the sensitive channel material to damaging functionalization processes.
Solution Approach 2:
The substrate surface acts as an intermediary between the deposition process and the carbon nanotube channel. By preparing the substrate surface with enhanced chemical activity through plasma or chemical treatment, the patent enables effective dielectric nucleation and growth without directly treating the channel material, thus protecting channel quality while facilitating deposition.
3Ease of manufacture
If deposition processes use energetic oxygen species or plasma, then dielectric material can be deposited, but graphene and CNT are vulnerable to degradation
Solution Approach 1:
The patent extracts the harmful plasma or oxygen species treatment from the channel material and applies it only to the substrate surface. By separating the treatment location, the patent maintains the benefits of energetic species for dielectric deposition while eliminating their harmful effects on the carbon nanotube channel.
Solution Approach 2:
The patent applies preliminary protective measures by limiting plasma or oxygen exposure to the substrate rather than the channel. This preliminary anti-action prevents degradation of the carbon nanotube by controlling where energetic species are introduced into the process.
4Length of stationary object
If spin-on gate dielectric is used to obtain very thin films, then thin films less than 10 nm can be obtained, but the gate dielectric quality is low and contains trapped charges and impurities
Solution Approach 1:
The gate dielectric is segmented into a first layer deposited by vapor deposition methods (providing high quality, low defect density) and a second layer that can be spin-on (providing thin film capability). This segmentation allows each layer to contribute its strengths: the first layer provides quality and the second layer enables thinness.
Solution Approach 2:
The patent uses composite gate dielectric structure combining different deposition methods. The first gate dielectric layer uses vapor deposition for high quality, while the second layer uses spin-on for thin film formation, creating a composite structure that achieves both thinness and acceptable quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the formation of a contiguous gate dielectric layer without pinholes, enhancing the quality and performance of field effect transistors by protecting the channel material and enabling the use of otherwise damaging microfabrication techniques.
Implementation Method 1
The disposable material layer shields and protects the graphene layer or the CNT during the deposition and patterning of the gate stack layer
Implementation Method 2
The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure
Implementation Method 3
The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT
Data Source
AI summary
A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.