Collective 3D Module Manufacturing via Groove Isolation

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Solution Overview

Problem

The existing methods for manufacturing 3D electronic modules face challenges such as component breakage due to excessive ultrasonic energy during connection and substrate bending during polymerization, leading to the inclusion of defective components in the final module.

Innovation Solution

A collective manufacturing method that involves testing and separating valid components on a shared substrate, using grooves to isolate and reconstitute a plate with only valid components, and forming wider grooves for clean conductive tracks, allowing for the stacking and interconnection of slices without defective components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ultrasonic energy is sent to connect pads directly, then connection is achieved, but component breakage occurs due to excessive energy

Engineering Contradiction:
Improveconnection qualityVSAvoidcomponent integrity
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent introduces an intermediate substrate that acts as a mediator between the component and the final connection point. The substrate absorbs excess ultrasonic energy during the connection process, preventing direct transmission of harmful energy to the component while still enabling reliable pad connections. This intermediary layer protects the component from breakage during the bonding process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the physical parameters of the connection process by heating the substrate to soften it, which changes its mechanical properties. The softened substrate becomes more compliant and absorbs ultrasonic energy more effectively, reducing the risk of component breakage. After connection, the substrate is rehardened, restoring its structural integrity.

Inventive Principle:
Principle #35Parameter changes

2Strength

If substrate is heated to soften and absorb ultrasonic energy, then component protection is improved, but connection difficulty increases

Engineering Contradiction:
Improvecomponent integrityVSAvoidconnection ease
Core Design Contradiction:
StrengthVSEase of manufacture

Solution Approach 1:

The patent employs periodic heating and cooling cycles of the substrate. The substrate is heated only during the ultrasonic connection phase to soften and absorb energy, then cooled and rehardened between connections to maintain structural stability. This periodic temperature variation allows the substrate to alternately provide energy absorption and structural support, resolving the contradiction between protection and connection ease.

Inventive Principle:
Principle #19Periodic action

3Reliability

If polymerization is carried out at 150°C, then component coating is achieved, but substrate bending occurs due to expansion coefficient difference

Engineering Contradiction:
Improvecoating qualityVSAvoidsubstrate flatness
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The patent changes the polymerization temperature parameter from 150°C to a lower temperature range that is compatible with the substrate's thermal expansion characteristics. By reducing the polymerization temperature, the differential thermal expansion between the component and substrate is minimized, preventing substrate bending while still achieving effective coating and encapsulation of the component.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If individual wafer testing is performed, then defective components are eliminated, but manufacturing efficiency decreases

Engineering Contradiction:
Improvemodule qualityVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges multiple individual wafer testing operations into a single collective testing operation. By maintaining good continuity of material between components and the substrate during manufacturing, the patent enables simultaneous electrical testing of multiple wafers stacked together. This collective testing approach identifies defective components across all wafers in one operation, eliminating the need for sequential individual testing and significantly improving manufacturing efficiency while maintaining quality assurance.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method ensures the production of 3D electronic modules with only valid components, maintaining material continuity and enabling collective electrical testing, thereby improving the reliability and efficiency of the stacking process.

Implementation Method 1

One method consists in directly connecting the pads of the component to those of the insulating substrate by sending ultrasound

Methodology Applied
Scientific EffectUltrasonic vibration: Ultrasonic Vibration

Implementation Method 2

One solution to reduce this energy consists in heating the substrate which then softens and absorbs part of the ultrasonic energy sent

Methodology Applied
Scientific EffectHeating: Heating

Implementation Method 3

during the coating of the components by polymerization carried out at approximately 150 °C

Methodology Applied
Scientific EffectPolymerization: Photopolymerisation

Data Source

PatentEP2054929B1Process for the collective manufacturing of electronic 3D modules
Publication Date: 2016.03.16 D PLUS
  • EP2054929B1 patent drawingFigure 1~3
  • EP2054929B1 patent drawingFigure 4~5
  • EP2054929B1 patent drawingFigure 6~8

AI summary

The invention relates to the collective manufacturing of n 3D modules. It comprises a manufacturing stage of a batch of n wafers i on the same plate, of the same thickness, and comprised of silicon, covered on one test point side face (20) then an insulating layer (4) of e thickness, forming the insulating substrate and equipped with at least one electronic component (11 ) connected to the test points (20) by means of the said insulating layer, with the components being separated from each other by primary grooves (30) with a width L1, and with the connecting points of the components (2) being connected to the tracks (3) that are flush with the level of the grooves (30), (B1) a stage depositing an adhesive support (40) on the component-side face, C1 ) a stage withdrawing the silicon plate (10) so as to show the test points (20), D1 ) a stage testing the electronic components of the plate by means of the test points (20), and marking of the valid components (11 '), E1 ), a stage for reporting on an adhesive film (41), the wafers (50) each comprising a valid component (11 '), with the wafers being separated by the secondary grooves (31) at the level at which the conductive tracks (3) of the valid components (11 ') appear. This stage, repeated K times, is followed by a stage of stacking the K plates, by making metalized holes in the thickness of the stack which are intended for connecting the wafers between the K plates, then cutting the stack to obtain the n 3D modules.