Collective Closed-Loop Cut for 3D Wiring Layers

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Solution Overview

Problem

The existing sidewall transfer process for manufacturing electronic components, particularly in resistive random access memory (ReRAM), requires multiple steps and masks for each layer of wiring, leading to increased complexity and cost due to the need for closed-loop cut processing for each layer.

Innovation Solution

A method is developed to collectively perform the closed-loop cut for multiple wiring layers in a single process, reducing the number of steps and masks required by forming and cutting the wiring layers in a closed-loop shape using sidewall transfer technology, where connection vias are formed to connect layers and the closed-loop cut is achieved through a single etching process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the sidewall transfer process is used to form wiring layers in a closed-loop shape, then the wiring structure is well-defined and surrounded by sidewalls, but the number of masks and process steps increases due to the need for closed-loop cut for each layer

Engineering Contradiction:
Improvewiring structure definitionVSAvoidnumber of masks and process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the closed-loop cut operations for multiple wiring layers into a single collective etching process. Instead of performing separate closed-loop cuts for each wiring layer (which would require multiple masks and process steps), the invention performs one unified etching operation that simultaneously cuts all wiring layers, thereby reducing process complexity while maintaining the precision of individual wiring structures

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal mask structure that serves multiple functions: it defines the closed-loop pattern for wiring layers and simultaneously enables collective cutting of multiple layers. The sidewall structure acts as a multi-functional element that guides the etching process across different wiring layers without requiring layer-specific masks, thus reducing the overall number of masks needed

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If closed-loop cut is performed for each wiring layer individually, then each layer is precisely cut, but the manufacturing cost and complexity increase due to multiple masks being required

Engineering Contradiction:
Improvelayer-by-layer cutting precisionVSAvoidmanufacturing cost and complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent combines multiple individual closed-loop cut operations into a single collective etching process. By using a unified mask structure and performing one etching operation that affects multiple wiring layers simultaneously, the invention maintains cutting precision while significantly reducing the number of masks required and lowering manufacturing complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a two-dimensional approach (separate masks for each layer) to a three-dimensional approach where a single mask structure operates across multiple layers. The collective etching process extends the cutting operation through the vertical dimension, allowing simultaneous processing of multiple wiring layers without requiring separate masks for each layer

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the number of steps and masks needed for the closed-loop cut, thereby decreasing manufacturing complexity and cost while maintaining the integrity of the wiring layers in a nonvolatile storage device with three-dimensionally laminated memory cells.

Implementation Method 1

selectively removing the base material with the sidewall film as a mask

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS8987909B2Method of manufacturing electronic component
Publication Date: 2015.03.24 KIOXIA CORP
  • US8987909B2 patent drawing
  • US8987909B2 patent drawing
  • US8987909B2 patent drawing

AI summary

According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.