Semiconductor Collector Layer Carrier Concentration Peak Positioning
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Solution Overview
Problem
The carrier concentration at the peak position in the collector layer of semiconductor devices is affected by contamination during manufacturing, leading to inconsistent device characteristics and increased switching loss.
Innovation Solution
A semiconductor device with a collector layer where the carrier concentration peak is positioned 1 μm or more from the surface of the substrate, and a collector electrode is formed in contact with the collector layer, while the manufacturing process includes ion implantation, annealing, and etching to minimize contamination effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the carrier concentration peak position is positioned close to the collector electrode to reduce switching loss, then the switching loss is reduced, but the carrier concentration becomes more susceptible to contamination during manufacturing
Solution Approach 1:
The patent positions the carrier concentration peak at a specific depth (1 μm or more from the surface) rather than at the surface level, transitioning the problem from a two-dimensional surface issue to a three-dimensional spatial distribution problem. This vertical positioning in the depth dimension protects the peak from surface contamination while maintaining its functional benefits.
Solution Approach 2:
The patent performs ion implantation and annealing processes beforehand to establish the carrier concentration peak at the desired depth position before the collector electrode formation. This preliminary establishment of the peak position ensures that subsequent manufacturing steps do not compromise the peak's carrier concentration.
2Reliability
If the carrier concentration at the peak position is reduced to improve device characteristics, then the device characteristics improve, but the carrier concentration becomes more affected by manufacturing atmosphere contamination
Solution Approach 1:
By positioning the carrier concentration peak at a depth of 1 μm or more from the surface, the patent moves the critical region away from the surface where contamination occurs. This spatial separation in the depth dimension protects the reduced carrier concentration region from contamination during manufacturing.
Solution Approach 2:
The patent creates a localized region with specific carrier concentration characteristics at a particular depth position, rather than uniformly distributing the carrier concentration. This local quality control allows the peak region to have optimized characteristics while being protected from contamination.
3Ease of manufacture
If the carrier concentration peak is positioned closer to the surface to simplify manufacturing, then the manufacturing process is simplified, but the carrier concentration is more susceptible to contamination
Solution Approach 1:
The patent solves the manufacturing complexity issue by using ion implantation and annealing processes that can precisely control the carrier concentration peak depth. This approach adds control in the depth dimension without significantly complicating the overall manufacturing flow, achieving both precision and manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the impact of contamination on the carrier concentration peak, allowing for controlled carrier concentration levels, lower switching loss, and improved manufacturing yield by positioning the carrier concentration peak away from the collector electrode, thus enabling high-speed operation and adjusting the Vce (sat)-Eoff trade-off curve over a wider range.
Implementation Method 1
a collector layer in which a position where a carrier concentration profile has a peak value is 1 μm or more from a surface of the semiconductor substrate
Implementation Method 2
ion implanting a bottom surface of the semiconductor substrate with a dopant
Implementation Method 3
forming a collector layer by activating the dopant by annealing
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a collector layer in which the carrier concentration is maximized at a carrier concentration peak position that is 1 μm or more from a surface of the semiconductor substrate. The semiconductor device further includes a collector electrode formed in contact with a surface of the collector layer.