Collector Mesa Tilting Side Faces for Thermal Resistance Reduction
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Solution Overview
Problem
Semiconductor devices with hetero-junction bipolar transistors experience degradation in characteristics due to increased temperature from self-heating during power amplification operations, and existing heat transfer methods are inefficient in reducing thermal resistance from transistors to bumps.
Innovation Solution
A semiconductor device design featuring a collector mesa with tilting side faces and an extended first-layer emitter line that covers both the top and side faces of the mesa, reducing thermal resistance by creating a more efficient heat transfer path to the bump.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the first-layer emitter line is extended to overlap with the tilting side faces of the collector mesa, then the thermal resistance of the heat transfer path is reduced, but the device complexity increases
Solution Approach 1:
The emitter line is extended from a conventional planar configuration to overlap with the tilting side faces of the collector mesa in the vertical dimension. This three-dimensional arrangement increases the contact area between the emitter line and the heat-generating regions of the transistor, thereby reducing thermal resistance without requiring additional layers or complex structures.
Solution Approach 2:
The heat transfer path is segmented into multiple contact regions: the emitter line contacts both the top face and the tilting side faces of the collector mesa. This segmentation allows heat to be conducted through multiple parallel paths, reducing the overall thermal resistance of the heat transfer path from the transistor to the bump.
2Productivity
If the operating frequency and output of the power amplifier are increased, then the productivity and power are improved, but the temperature of the transistors increases due to increased heat generation
Solution Approach 1:
The tilting side faces of the collector mesa, which are byproducts of the etching process, are utilized as additional heat transfer surfaces. The emitter line is configured to overlap with these faces, converting what would be wasted surface area into beneficial thermal conduction paths, thereby reducing transistor temperature even at high operating frequencies and output levels.
3Temperature
If the collector mesa has tilting side faces, then the heat transfer area is increased, but the manufacturing precision requirements are increased
Solution Approach 1:
The emitter line is designed with specific dimensional parameters to ensure adequate overlap with the tilting side faces of the collector mesa. By optimizing the width and position of the emitter line, sufficient thermal contact is achieved while maintaining compatibility with conventional manufacturing tolerances, thus balancing heat transfer efficiency with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces thermal resistance, suppressing the degradation of transistor characteristics by enhancing heat dissipation, thereby maintaining performance across varying operating frequencies and output levels.
Implementation Method 1
The first-layer emitter line composes part of a heat transfer path from the transistor to the bump. Since the first-layer emitter line extends from the area where the first-layer emitter line is overlapped with the top face of the collector mesa to the areas where the first-layer emitter line is overlapped with at least part of the tilting side faces of the collector mesa in a plan view, the thermal resistance of the heat transfer path from the transistor to the bump is reduced.
Data Source
AI summary
At least one transistor is arranged on a substrate. A collector layer and a base layer of the transistor compose a collector mesa having a substantially mesa shape and the collector mesa has side faces tilting with respect to the substrate so that the dimension of a top face in a first direction of a plane of the substrate is smaller than the dimension of a bottom face therein. A first insulating film covering the transistor is arranged on the substrate. A first-layer emitter line that extends from an area overlapped with the top face of the collector mesa to areas overlapped with at least part of the tilting side faces of the collector mesa in a plan view is arranged on the first insulating film. A second-layer emitter line and an emitter bump are arranged on the first-layer emitter line.