Integrated Circuit Design Using Colorless Routing for Triple Patterning Lithography
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Solution Overview
Problem
The complexity of design rules in integrated circuits has increased, requiring more sophisticated patterning technologies like triple patterning lithography (TPL), which demands precise arrangement of patterns with space constraints to avoid color violations during semiconductor manufacturing.
Innovation Solution
A computer-implemented method that places standard cells based on design data, generates layouts through colorless routing, and assigns colors to patterns in a TPL layer, ensuring minimum spaces between them to prevent color violations, and subsequently creates masks for semiconductor device manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If triple patterning lithography (TPL) is used to reduce gaps between adjacent patterns, then manufacturing precision is improved, but device complexity increases due to the need for multiple masks and color decomposition
Solution Approach 1:
The patterning process is segmented into three separate lithography steps, each using a different mask (first, second, and third masks). Each mask forms a specific subset of the final pattern, allowing precise control over gap dimensions while distributing the complexity across multiple manageable stages rather than attempting to form all patterns in a single step
Solution Approach 2:
Color decomposition is performed as a preliminary action before mask generation. The TPL layer patterns are pre-assigned to different color groups based on their spatial relationships and gap requirements, which guides the subsequent mask design process and ensures that the three masks can be generated without color violations while maintaining precise gap control
2Manufacturing precision
If color decomposition is performed for TPL, then manufacturing precision is improved through better pattern control, but ease of operation deteriorates due to additional constraints and rules
Solution Approach 1:
Color assignment acts as an intermediary layer between the geometric pattern arrangement and the final mask generation. By introducing color as an intermediate attribute that mediates the relationship between patterns and masks, the system achieves precise pattern control through color-based constraints while automating the complexity of multi-mask generation, thereby improving ease of operation despite the added precision requirements
3Manufacturing precision
If multiple masks are used for patterning, then manufacturing precision is improved, but productivity decreases due to increased process steps
Solution Approach 1:
The patent merges the color decomposition analysis and mask generation operations into a unified automated workflow. By combining these previously separate steps into an integrated process that simultaneously considers color assignments, space constraints, and mask design, the system maintains high manufacturing precision through multiple masks while improving productivity by eliminating manual intervention and reducing the total number of discrete process steps
Data Source
AI summary
A computer-implemented method compresses placing standard cells based on design data defining an integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which a first pattern, a second pattern, and a third pattern in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a non-transitory computer-readable storage medium. The space constraints define minimum spaces between the first pattern, the second pattern, and the third pattern. A color violation does not occur between the first pattern, second pattern, and the third pattern. A first mask, a second mask, and a third mask are generated based on the layout. A semiconductor device is manufactured by using the generated first mask, the second mask, and the third mask.