Column AD Conversion Units with Shared Delay Circuit for Imaging
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Solution Overview
Problem
The existing column ADC type solid-state imaging devices using the single slope type AD conversion method face limitations in resolution improvement, as the number of phase information items increases exponentially without a linear increase in resolution, leading to inefficiencies in analog-to-digital conversion.
Innovation Solution
The proposed imaging device incorporates multiple column delay units and column AD conversion units, each with a comparison unit, latch unit, and counter unit, utilizing a reference signal and multiple clocks to enhance AD conversion accuracy by synchronizing the delay circuit and reference signal generation, thereby improving resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of phase information items is increased to improve resolution, then AD conversion accuracy is improved, but the number of required circuits increases exponentially
Solution Approach 1:
The patent divides the column AD conversion units into multiple groups, with each group sharing a common delay circuit. This segmentation allows multiple column AD conversion units to share resources, reducing the overall number of circuits while maintaining high resolution. Specifically, the delay circuit is shared among multiple column AD conversion units, eliminating the need for separate delay circuits for each unit.
Solution Approach 2:
The delay circuit is designed to serve multiple functions and multiple column AD conversion units simultaneously. By making the delay circuit universal and shareable across different column AD conversion units, the patent reduces circuit complexity while maintaining the ability to achieve high-resolution AD conversion through multiple phase information items.
2Measurement precision
If multiple column delay units are provided for each column AD conversion unit to improve resolution, then AD conversion accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the delay circuit functionality into a shared resource that serves multiple column AD conversion units. Instead of providing separate delay circuits for each column AD conversion unit, the invention combines them into a common delay circuit that can be utilized by multiple units, thereby reducing device complexity and power consumption while maintaining high AD conversion accuracy.
Solution Approach 2:
The patent implements dynamic control of the delay circuit through a selection unit that can selectively connect different column AD conversion units to the shared delay circuit. This dynamic allocation allows the system to optimize resource usage, reducing the number of active circuits at any given time while maintaining the capability for high-resolution conversion when needed.
3Measurement precision
If the delay circuit and reference signal are not synchronized, then circuit design is simpler, but jitter increases and AD conversion accuracy deteriorates
Solution Approach 1:
The patent implements a synchronization mechanism where the delay circuit is controlled to be synchronized with the reference signal. This feedback-based synchronization ensures that the delay circuit operates in harmony with the reference signal, minimizing jitter and maintaining high AD conversion accuracy. The selection unit and control logic provide the necessary feedback control to maintain synchronization.
4Measurement precision
If more column delay units are provided to reduce jitter, then AD conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The patent employs dynamic resource allocation where the shared delay circuit is activated only when needed by specific column AD conversion units. The selection unit dynamically connects only the necessary circuits during each conversion cycle, reducing overall power consumption compared to having all delay circuits continuously active. This dynamic approach maintains high AD conversion accuracy while minimizing energy usage.
Solution Approach 2:
The patent implements a time-division multiplexing approach where the shared delay circuit serves different column AD conversion units at different times. When one unit is using the delay circuit, others are idle or using alternative resources. This approach allows the system to recover power that would otherwise be consumed by continuously operating multiple delay circuits, while maintaining the capability for high-accuracy conversion.
Data Source
AI summary
An imaging device includes an imaging unit, a reference signal generation unit, m (m is an integer of 3 or more) number of column delay units, and a plurality of column AD conversion units. The plurality of column delay units is arranged so as to correspond to two or more and less than m of the column AD conversion units. Each of the plurality of column delay units includes a first delay circuit. The first delay circuit generates a plurality of first delay clocks. The column AD conversion unit includes a comparison unit, a latch unit, and a counter unit. The comparison unit compares a pixel signal with a reference signal, and outputs a control signal corresponding to a comparison result. The latch unit includes a plurality of latch circuits that latches the plurality of first delay clocks on the basis of a state change of the control signal.