Column-Parallel A/D Circuit Offset Timing for Low-Light Linearity
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Solution Overview
Problem
In CMOS image sensors, the linearity at low illuminance is compromised due to large IR-drop during the first A/D conversion, leading to errors in latch timing and deteriorated color balance and shading correction accuracy.
Innovation Solution
A solid-state image sensing device with a column-parallel A/D converting circuit that includes a first A/D converter with an offset generating circuit, and a reference-voltage generating circuit producing a ramp-wave reference voltage, which reduces IR-drop by shifting the timing of A/D conversion and improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital correlated double sampling is used to remove circuit offset, then offset removal is achieved, but large IR-drop occurs during first A/D conversion causing latch timing errors
Solution Approach 1:
The patent applies preliminary action by performing the first A/D conversion in a dark state before the second A/D conversion in an illumination state. This preliminary dark state conversion allows the system to capture and subtract the circuit offset (including IR-drop effects) from the final illumination state measurement, thereby removing the harmful offset while maintaining timing precision through correlated double sampling.
Solution Approach 2:
The patent converts the harmful IR-drop effect into a beneficial offset component. By capturing the IR-drop during the dark state first conversion and then subtracting it from the illumination state measurement, the system transforms the previously harmful voltage shift into a measurable offset that can be removed through correlation, improving overall measurement accuracy.
2Productivity
If all A/D converting circuits are simultaneously driven in first A/D conversion, then dark image acquisition is completed, but potential shifts of power supply voltage and ground voltage largely occur
Solution Approach 1:
The system performs preliminary action by executing the first A/D conversion for all columns simultaneously in a dark state to acquire the dark image. This preliminary acquisition is necessary for offset removal, and the patent accepts the temporary voltage instability during this phase because the correlated double sampling will subsequently remove the resulting offset from the final illumination state measurement.
3Manufacturing precision
If ramp-wave reference voltage is generated to reduce IR-drop, then linearity at low illuminance is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by generating a ramp-wave reference voltage that varies over time instead of using a constant reference voltage. This time-varying reference voltage parameter allows the A/D conversion to compensate for IR-drop effects, improving linearity at low illuminance. The ramp waveform is generated using standard circuit elements (resistors, capacitors, switches) integrated into the existing A/D converter structure.
Data Source
AI summary
A technique capable of improving linearity at a low illuminance is provided. A solid-state sensing image device includes: a pixel array including a plurality pixels arranged in a matrix form and a plurality of pixel signal lines connected to the plurality of pixels and receiving pixel signals supplied from the plurality pixels; a column-parallel A/D converting circuit connected to the plurality of pixel signal lines; and a reference-voltage generating circuit generating ramp-wave reference voltage that linearly changes in accordance with time passage. The column-parallel A/D converting circuit includes a first A/D converter, the first A/D converter includes: a first input terminal connected to the pixel signal line; a second input terminal receiving the reference voltage; and an offset generating circuit connected to the first input terminal and generating an offset voltage for the first input terminal.