Column ADC Bit Inconsistency Prevention in CMOS Image Sensors
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Solution Overview
Problem
CMOS image sensors with column parallel output type ADCs face bit inconsistency issues due to metastability at data change points between low-level and high-level bit counters, leading to potential erroneous counting.
Innovation Solution
The implementation of a bit inconsistency prevention circuit and Gray code counters in the column ADC, which synchronizes the standard clock and performs counting operations without low-level bit operations, reducing power consumption and preventing bit inconsistency by using a Gray code counter configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a full bit ripple counter is used for AD conversion in column parallel ADC, then AD conversion function is achieved, but bit inconsistency and metastability occur between low-level and high-level bit counters
Solution Approach 1:
The patent divides the counter into two separate sections: a low-level bit latch section and a high-level bit counting section. This segmentation allows each section to operate independently with optimized functionality, preventing bit inconsistency between sections while maintaining overall AD conversion accuracy.
Solution Approach 2:
The patent introduces a bit inconsistency prevention section that acts as an intermediary between the low-level bit latch section and the high-level bit counting section. This intermediary component synchronizes the standard clock and coordinates the operations of both sections, eliminating metastability and bit inconsistency issues.
2Measurement precision
If standard clock synchronization is implemented across all column lines, then temporal resolution is improved, but power consumption increases
Solution Approach 1:
The patent segments the clocking strategy by applying standard clock synchronization only to the high-level bit counting section, while the low-level bit latch section uses a different timing approach. This selective synchronization maintains high temporal resolution where needed while reducing overall power consumption.
Solution Approach 2:
The patent applies different quality characteristics to different parts of the system: standard clock synchronization is applied locally to the high-level bit counting section where temporal resolution is critical, while other sections use less power-intensive timing mechanisms.
Data Source
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AI summary
A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a bit inconsistency prevention section configured to prevent bit inconsistency between output of a low-level bit latch section and a high-level bit counting section.