Column ADC Imaging Circuit With Buffered Counter Timing

A delay adjustment circuit is introduced as an intermediary component between the counter and the storing units. This circuit includes a delay adjustment unit that can compensate for propagation delays and a switch unit that selects between different delay states. The intermediary circuit enables precise timing control without requiring complex synchronized clock distribution or multiple counters, thus improving measurement precision while maintaining reasonable device complexity.

Buffers are strategically placed before the storing units to pre-stabilize count values. The first buffer is positioned between the delay adjustment circuit and the first storing unit, while the second buffer is positioned between the delay adjustment circuit and the second storing unit. This preliminary action ensures that count values are stabilized before being stored, preventing propagation delay variations from introducing fixed noise components. The buffer placement is optimized to achieve stability with minimal additional complexity.

The delay adjustment circuit changes the timing parameter of count pulse propagation by introducing controllable delays. The delay adjustment unit can modify the propagation delay of count pulses to different storing units, thereby equalizing the timing parameters across columns. This parameter change approach allows the system to compensate for inherent propagation delay differences without requiring complex structural modifications, maintaining ease of manufacture while eliminating fixed noise components that would otherwise degrade image quality.